Cypress Semiconductor CY7C028V Hoja de especificaciones - Página 11
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Switching Waveforms
A
–A
0
2
SEM
I/O
0
t
SA
R/W
OE
A
–A
0L
2L
R/W
L
SEM
L
A
–A
0R
2R
R/W
R
SEM
R
Notes
29. CE = HIGH for the duration of the above timing (both write and read cycle).
30. I/O
= I/O
= LOW (request semaphore); CE
0R
0L
31. Semaphores are reset (available to both ports) at cycle start.
32. If t
is violated, the semaphore is definitely obtained by one side or the other, but which side gets the semaphore is unpredictable.
SPS
Document #: 38-06078 Rev. *B
(continued)
Figure 9. Semaphore Read After Write Timing, Either Side
VALID ADRESS
t
AW
t
HA
t
SCE
t
SD
DATA
VALID
IN
t
HD
t
PWE
WRITE CYCLE
Figure 10. Timing Diagram of Semaphore Contention
MATCH
t
SPS
MATCH
= CE
= HIGH.
R
L
CY7C027V/027VN/027AV/028V
t
SAA
VALID ADRESS
t
ACE
t
SOP
t
t
SWRD
DOE
t
SOP
READ CYCLE
[30, 31, 32]
CY7C037V/037AV/038V
[29]
t
OHA
DATA
VALID
OUT
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