Cypress Semiconductor CY7C1018DV33 Hoja de especificaciones - Página 5
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Data Retention Characteristics
Parameter
V
V
for Data Retention
DR
CC
I
Data Retention Current
CCDR
[3]
t
Chip Deselect to Data Retention Time
CDR
[12]
t
Operation Recovery Time
R
Data Retention Waveform
V
CC
CE
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled)
ADDRESS
DATA OUT
PREVIOUS DATA VALID
Read Cycle No. 2 (OE Controlled)
ADDRESS
CE
OE
HIGH IMPEDANCE
DATA OUT
V
t
CC
PU
SUPPLY
CURRENT
Notes
12. Full device operation requires linear V
13. Device is continuously selected. OE, CE = V
14. WE is HIGH for Read cycle.
15. Address valid prior to or coincident with CE transition LOW.
Document #: 38-05465 Rev. *D
(Over the Operating Range)
Description
V
V
3.0V
t
CDR
[13, 14]
t
AA
t
OHA
[14, 15]
t
RC
t
ACE
t
DOE
t
LZOE
t
LZCE
50%
> 50 µs or stable at V
ramp from V
to V
CC
DR
CC(min.)
.
IL
Conditions
= V
= 2.0V, CE > V
– 0.3V,
CC
DR
CC
> V
– 0.3V or V
< 0.3V
IN
CC
IN
DATA RETENTION MODE
>
V
2V
DR
t
RC
RC
DATA VALID
> 50 µs.
CC(min.)
CY7C1018DV33
Min.
Max.
Unit
2
V
3
mA
0
ns
t
ns
RC
3.0V
t
R
DATA VALID
t
HZOE
t
HZCE
HIGH
IMPEDANCE
t
PD
ICC
50%
ISB
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