Cypress Semiconductor CY7C1024DV33 Hoja de especificaciones - Página 4

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OUTPUT
Z 0 = 50Ω
(a)
*Capacitive Load consists of all
components of the test environment
AC Switching Characteristics
[5]
Over the Operating Range
Parameter
Read Cycle
[6]
t
V
(Typical) to the First Access
power
CC
t
Read Cycle Time
RC
t
Address to Data Valid
AA
t
Data Hold from Address Change
OHA
t
CE Active LOW to Data Valid
ACE
t
OE LOW to Data Valid
DOE
t
OE LOW to Low Z
LZOE
t
OE HIGH to High Z
HZOE
t
CE Active LOW to Low Z
LZCE
t
CE Deselect HIGH to High Z
HZCE
t
CE Active LOW to Power Up
PU
t
CE Deselect HIGH to Power Down
PD
Notes
4. Valid SRAM operation does not occur until the power supplies have reached the minimum operating V
V
, normal SRAM operation can begin including reduction in V
DD
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, and input pulse levels of 0 to 3.0V. Test conditions for the read cycle use
output loading as shown in part a) of
6. t
gives the minimum amount of time that the power supply is at typical V
POWER
7. t
, t
, t
, t
, t
, and t
HZOE
HZCE
HZWE
LZOE
LZCE
voltage.
8. These parameters are guaranteed by design and are not tested.
Document Number: 001-08353 Rev. *C
Figure 2. AC Test Loads and Waveform
50Ω
= 1.5V
V
TH
30 pF*
3.0V
90%
10%
GND
Rise Time > 1V/ns
Description
[3]
[7]
[7]
[3, 7]
[3, 7]
[3, 8]
[3, 8]
to the data retention (V
DD
Figure
2, unless specified otherwise.
are specified with a load capacitance of 5 pF as in part (b) of
LZWE
[4]
All input pulses
90%
10%
Fall Time:> 1V/ns
(c)
(3.0V). 100 μs (t
DD
, 2.0V) voltage.
CCDR
values until the first memory access is performed.
CC
2. Transition is measured ±200 mV from steady state
Figure
CY7C1024DV33
R1 317 Ω
3.3V
OUTPUT
5 pF*
*
Including jig
and scope
(b)
–10
Min
Max
100
10
10
3
10
5
1
5
3
5
0
10
) after reaching the minimum operating
power
Page 4 of 9
R2
351Ω
Unit
μs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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