Cypress Semiconductor CY7C1298H Hoja de especificaciones - Página 4

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Pin Descriptions

Pin
Type
A0, A
, A
Input-
1
Synchronous
BW
Input-
[A:B]
Synchronous
GW
Input-
Synchronous
BWE
Input-
Synchronous
CLK
Input-
Clock
CE
Input-
1
Synchronous
CE
Input-
2
Synchronous
CE
Input-
3
Synchronous
OE
Input-
Asynchronous
ADV
Input-
Synchronous
ADSP
Input-
Synchronous
ADSC
Input-
Synchronous
ZZ
Input-
Asynchronous
DQs
I/O-
Synchronous
DQP
[A:B]
V
Power Supply Power supply inputs to the core of the device.
DD
V
Ground
SS
V
I/O Power
DDQ
Supply
V
I/O Ground
SSQ
MODE
Input-
Static
NC
Document #: 38-05665 Rev. *B
Address Inputs used to select one of the 64K address locations. Sampled at the rising edge
of the CLK if ADSP or ADSC is active LOW, and CE
fed to the two-bit counter.
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM.
Sampled on the rising edge of CLK.
Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global
write is conducted (ALL bytes are written, regardless of the values on BW
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be
asserted LOW to conduct a byte write.
Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst
counter when ADV is asserted LOW, during a burst operation.
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE
and CE
to select/deselect the device. ADSP is ignored if CE
2
3
when a new external address is loaded.
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with
CE
and CE
to select/deselect the device. CE
1
3
loaded.
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE
and CE
to select/deselect the device. CE
1
2
loaded.
Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When
LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as
input data pins. OE is masked during the first clock of a read cycle when emerging from a deselected
state.
Advance Input signal, sampled on the rising edge of CLK, active LOW. When asserted, it
automatically increments the address in a burst cycle.
Address Strobe from Processor, sampled on the rising edge of CLK, active LOW. When
asserted LOW, addresses presented to the device are captured in the address registers. A
also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recog-
nized. ASDP is ignored when CE
Address Strobe from Controller, sampled on the rising edge of CLK, active LOW. When
asserted LOW, addresses presented to the device are captured in the address registers. A
also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recog-
nized.
ZZ "sleep" Input, active HIGH. When asserted HIGH places the device in a non-time-critical
"sleep" condition with data integrity preserved. For normal operation, this pin has to be LOW or left
floating. The ZZ pin has an internal pull-down.
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by
the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified
by the addresses presented during the previous clock rise of the read cycle. The direction of the
pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs
and DQP
are placed in a tri-state condition.
[A:B]
Ground for the core of the device.
Power supply for the I/O circuitry.
Ground for the I/O circuitry.
Selects Burst Order. When tied to GND selects linear burst sequence. When tied to V
floating selects interleaved burst sequence. This is a strap pin and should remain static during
device operation. Mode Pin has an internal pull-up.
No Connects. Not internally connected to the die. 2M, 4M, 9M, 18M, 72M, 144M, 288M, 576M and
1G are address expansion pins and are not internally connected to the die.
Description
, CE
, and CE
1
2
is sampled only when a new external address is
2
is sampled only when a new external address is
3
is deasserted HIGH.
1
CY7C1298H
are sampled active. A
are
3
[1:0]
and BWE).
[A:B]
is HIGH. CE
is sampled only
1
1
are
[1:0]
are
[1:0]
or left
DD
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