Cypress Semiconductor CY7C1302DV25 Hoja de especificaciones - Página 3

Navegue en línea o descargue pdf Hoja de especificaciones para Hardware informático Cypress Semiconductor CY7C1302DV25. Cypress Semiconductor CY7C1302DV25 19 páginas. Cypress 9-mbit burst of two pipelined srams with qdrtm architecture specification sheet

Imprimir página
Pin Definitions
(continued)
Name
I/O
C
Input-
Clock
C
Input-Clock
K
Input-Clock
K
Input-Clock
ZQ
Input
TDO
Output
TCK
Input
TDI
Input
TMS
Input
NC/18M
N/A
NC/36M
N/A
GND/72M
Input
GND/144M
Input
NC
N/A
V
Input-
REF
Reference
V
Power Supply Power supply inputs to the core of the device.
DD
V
Ground
SS
V
Power Supply Power supply inputs for the outputs of the device.
DDQ
Introduction
Functional Overview
The CY7C1302DV25 is a synchronous pipelined Burst SRAM
equipped with both a Read port and a Write port. The Read
port is dedicated to Read operations and the Write port is
dedicated to Write operations. Data flows into the SRAM
through the Write port and out through the Read port. These
devices multiplex the address inputs in order to minimize the
number of address pins required. By having separate Read
and Write ports, the QDR-I completely eliminates the need to
"turn-around" the data bus and avoids any possible data
contention, thereby simplifying system design. 38-05625
Accesses for both ports are initiated on the rising edge of the
Positive Input Clock (K). All synchronous input timing is refer-
enced from the rising edge of the input clocks (K and K) and
all output timing is referenced to the output clocks (C and C,
or K and K when in single clock mode).
All synchronous data inputs (D
registers controlled by the input clocks (K and K). All
Document #: 38-05625 Rev. *A
Positive Input Clock for Output Data. C is used in conjunction with C to clock out the Read data
from the device. C and C can be used together to deskew the flight times of various devices on
the board back to the controller. See application example for further details.
Negative Input Clock for Output Data. C is used in conjunction with C to clock out the Read data
from the device. C and C can be used together to deskew the flight times of various devices on
the board cack to the controller. See application example for further details.
Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the
device and to drive out data through Q
on the rising edge of K.
Negative Input Clock Input. K is used to capture synchronous inputs being presented to the
device and to drive out data through Q
Output Impedance Matching Input. This input is used to tune the device outputs to the system
data bus impedance. Q
output impedance is set to 0.2 x RQ, where RQ is a resistor connected
[17:0]
between ZQ and ground. Alternately, this pin can be connected directly to V
the minimum impedance mode. This pin cannot be connected directly to GND or left unconnected.
TDO for JTAG.
TCK pin for JTAG.
TDI pin for JTAG.
TMS pin for JTAG.
Address expansion for 18M. This is not connected to the die and so can be tied to any voltage
level.
Address expansion for 36M. This is not connected to the die and so can be tied to any voltage
level.
Address expansion for 72M. This must be tied LOW.
Address expansion for 144M. This must be tied LOW.
Not connected to the die. Can be tied to any voltage level.
Reference Voltage Input. Static input used to set the reference level for HSTL inputs and Outputs
as well as AC measurement points.
Ground for the device.
) pass through input
[17:0]
Description
when in single clock mode. All accesses are initiated
[17:0]
when in single clock mode.
[17:0]
synchronous data outputs (Q
registers controlled by the rising edge of the output clocks (C
and C, or K and K when in single clock mode).
All synchronous control (RPS, WPS, BWS
through input registers controlled by the rising edge of input
clocks (K and K).
Read Operations
The CY7C1302DV25 is organized internally as 2 arrays of
256K x 18. Accesses are completed in a burst of two
sequential 18-bit data words. Read operations are initiated by
asserting RPS active at the rising edge of the positive input
clock (K). The address is latched on the rising edge of the K
clock. Following the next K clock rise the corresponding lower
order 18-bit word of data is driven onto the Q
the output timing reference. On the subsequent rising edge of
C the higher order data word is driven onto the Q
requested data will be valid 2.5 ns from the rising edge of the
output clock (C and C, or K and K when in single clock mode,
167-MHz device).
CY7C1302DV25
, which enables
DDQ
) pass through output
[17:0]
) inputs pass
[1:0]
using C as
[17:0]
. The
[17:0]
Page 3 of 18
[+] Feedback