Cypress Semiconductor CY7C1329H Hoja de especificaciones - Página 13
Navegue en línea o descargue pdf Hoja de especificaciones para Hardware informático Cypress Semiconductor CY7C1329H. Cypress Semiconductor CY7C1329H 17 páginas. 2-mbit (64k x 32) pipelined sync sram
Imprimir páginaSwitching Waveforms
[17, 19, 20]
Read/Write Cycle Timing
t CYC
CLK
t CL
t CH
t ADS
t ADH
ADSP
ADSC
t AS
t AH
ADDRESS
A1
A2
BWE,
BW[A:D]
t CES
t CEH
CE
ADV
OE
Data In (D)
High-Z
t CLZ
Data Out (Q)
Q(A1)
High-Z
Back-to-Back READs
Notes:
19. The data bus (Q) remains in High-Z following a Write cycle unless an ADSP, ADSC, or ADV cycle is performed.
20. GW is HIGH.
Document #: 38-05673 Rev. *B
(continued)
A3
A4
t WES
t WEH
t CO
t DS
t DH
D(A3)
t OEHZ
Q(A2)
Single WRITE
DON'T CARE
t OELZ
Q(A4)
Q(A4+1)
Q(A4+2)
BURST READ
UNDEFINED
CY7C1329H
A5
A6
D(A5)
D(A6)
Q(A4+3)
Back-to-Back
WRITEs
Page 13 of 16
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