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Cypress Semiconductor Perform CY62147EV30 Manual

Product Portfolio

Product
Range
CY62147EV30LL
Ind'l/Auto-A
Auto-E

Pin Configuration

Figure 1. 48-Ball VFBGA (Single Chip Enable)
1
2
3
A
BLE
OE
0
A
IO
BHE
3
8
IO
A
IO
5
9
10
IO
A
V
11
17
SS
V
IO
NC
CC
12
A
IO
IO
14
13
14
IO
A
NC
15
12
A
A
NC
9
8
Notes
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
3. NC pins are not connected on the die.
4. Pins H1, G2, and H6 in the BGA package are address expansion pins for 8 Mb, 16 Mb, and 32 Mb, respectively.
Document #: 38-05440 Rev. *G
V
Range (V)
CC
[2]
Min
Typ
Max
2.2
3.0
3.6
2.2
3.0
3.6
[3, 4]
4
5
6
A
A
NC
A
1
2
A
B
CE
IO
4
0
C
A
IO
IO
6
1
2
V
A
IO
D
CC
7
3
A
IO
V
E
SS
16
4
A
IO
IO
F
15
5
6
A
IO
WE
G
13
7
A
A
NC
H
10
11
Figure 3. 44-Pin TSOP II
A
1
4
A
2
3
A
3
2
A
4
1
A
5
0
6
CE
IO
7
0
IO
8
1
IO
9
2
IO
10
3
V
11
CC
V
12
SS
IO
13
4
IO
14
5
IO
15
6
IO
16
7
WE
17
A
18
17
A
19
16
A
20
15
A
21
14
A
22
13
CY62147EV30 MoBL
Power Dissipation
Speed
Operating I
CC
(ns)
f = 1 MHz
[2]
Typ
Max
Typ
45 ns
2
2.5
55 ns
2
3
Figure 2. 48-Ball VFBGA (Dual Chip Enable)
1
2
3
A
OE
BLE
IO
BHE
A
8
A
IO
IO
9
10
V
IO
A
11
SS
17
V
IO
NC
CC
12
A
IO
IO
14
14
13
A
IO
NC
12
15
A
A
NC
8
[3]
A
44
5
A
43
6
A
42
7
OE
41
40
BHE
39
BLE
38
IO
15
IO
37
14
IO
36
13
IO
35
12
34
V
SS
33
V
CC
32
IO
11
IO
31
10
IO
30
9
IO
29
8
28
NC
27
A
8
26
A
9
25
A
10
24
A
11
23
A
12
= V
CC
(mA)
Standby I
SB2
f = f
max
[2]
[2]
Max
Typ
Max
15
20
1
15
25
1
[3, 4]
4
5
6
A
A
CE
A
0
1
2
2
A
CE
B
IO
4
3
1
0
A
C
IO
IO
5
6
1
2
V
A
IO
D
CC
7
3
A
IO
V
E
16
4
SS
A
IO
IO
F
15
5
6
A
IO
WE
G
13
7
A
A
NC
H
9
10
11
, T
= 25°.
CC(typ)
A
Page 2 of 13
®
(μA)
7
20
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