Cypress Semiconductor Perform CY7C146 Manual - Página 9
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Imprimir páginaSwitching Waveforms
Figure 8. Write Cycle No. 2 (R/W Three-States Data I/Os—Either Port)
ADDRESS
CE
R/W
DATA
IN
D
OUT
CE
Valid First:
L
ADDRESS
L,R
CE
L
CE
R
BUSY
R
CE
Valid First:
R
ADDRESS
L,R
CE
R
CE
L
BUSY
L
Note
21. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in a high impedance state.
Document #: 38-06031 Rev. *E
(continued)
t
WC
t
SCE
t
AW
t
SA
t
HZWE
Figure 9. Busy Timing Diagram No. 1 (CE Arbitration)
ADDRESS MATCH
t
PS
t
ADDRESS MATCH
t
PS
t
CY7C136A, CY7C142, CY7C146
t
PWE
t
SD
DATA VALID
HIGH IMPEDANCE
t
BLC
BHC
t
BLC
BHC
CY7C132, CY7C136
[12, 21]
t
HA
t
HD
t
LZWE
Page 9 of 15
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