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nvSRAM Operation

nvSRAM

The STK14D88 nvSRAM is made up of two functional compo-

nents paired in the same physical cell. These are the SRAM

memory cell and a nonvolatile QuantumTrap™ cell. The SRAM

memory cell operates like a standard fast static RAM. Data in the

SRAM can be transferred to the nonvolatile cell (the STORE

operation), or from the nonvolatile cell to SRAM (the RECALL

operation). This unique architecture allows all cells to be stored

and recalled in parallel. During the STORE and RECALL opera-

tions SRAM READ and WRITE operations are inhibited. The

STK14D88 supports unlimited read and writes like a typical

SRAM. In addition, it provides unlimited RECALL operations

from the nonvolatile cells and up to 200K STORE operations.

SRAM READ

The STK14D88 performs a READ cycle whenever E and G are

low while W and HSB are high. The address specified on pins

determine which of the 32,768 data bytes will be accessed.

0-16

When the READ is initiated by an address transition, the outputs

will be valid after a delay of t

AVQV

is initiated by E and G, the outputs will be valid at t

, whichever is later (READ cycle #2). The data outputs will

GLQV

repeatedly respond to address changes within the t

time without the need for transitions on any control input pins,

and will remain valid until another address change or until either

E or G is brought high, or W or HSB is brought low.

SRAM WRITE

A WRITE cycle is performed whenever E and W are low and HSB

is high. The address inputs must be stable prior to entering the

WRITE cycle and must remain stable until either E or W goes

high at the end of the cycle. The data on the common I/O pins

will be written into memory if it is valid t

0-7

end of a W controlled WRITE or t

controlled WRITE.

It is recommended that G be kept high during the entire WRITE

cycle to avoid data bus contention on common I/O lines. If G is

left low, internal circuitry will turn off the output buffers t

goes low.

AutoStore Operation

The STK14D88 stores data to nvSRAM using one of three

storage operations. These three operations are Hardware Store

(activated by HSB), Software Store (activated by an address

sequence), and AutoStore (on power down).

AutoStore operation is a unique feature of Cypress Quantum

Trap technology is enabled by default on the STK14D88.

During normal operation, the device will draw current from V

to charge a capacitor connected to the V

charge will be used by the chip to perform a single STORE

operation. If the voltage on the V

the part will automatically disconnect the V

STORE operation will be initiated with power provided by the

capacitor.

CAP

Figure 12

shows the proper connection of the storage capacitor

) for automatic store operation. Refer to the DC CHARAC-

CAP

TERISTICS table for the size of the capacitor. The voltage on the

Document Number: 001-52037 Rev. **

(READ cycle #1). If the READ

or at

ELQV

access

AVQV

before the

DVWH

before the end of an E

DVEH

after

WLQZ

pin. This stored

CAP

pin drops below VSWITCH,

pin from V

. A

CAP

pin is driven to 5V by a charge pump internal to the chip. A

CAP

pull up should be placed on W to hold it inactive during power up.

To reduce unneeded nonvolatile stores, AutoStore and

Hardware Store operations will be ignored unless at least one

WRITE operation has taken place since the most recent STORE

or RECALL cycle. Software initiated STORE cycles are

performed regardless of whether a WRITE operation has taken

place. The HSB signal can be monitored by the system to detect

an AutoStore cycle is in progress.

Figure 12. AutoStore Mode

CAP

Hardware STORE (HSB) Operation

The STK14D88 provides the HSB pin for controlling and

acknowledging the STORE operations. The HSB pin can be

used to request a hardware STORE cycle. When the HSB pin is

driven low, the STK14D88 will conditionally initiate a STORE

operation after t

. An actual STORE cycle will only begin if

DELAY

a WRITE to the SRAM took place since the last STORE or

RECALL cycle. The HSB pin has a very resistive pull up and is

internally driven low to indicate a busy condition while the

STORE (initiated by any means) is in progress. This pin should

be externally pulled up if it is used to drive other inputs.

SRAM READ and WRITE operations that are in progress when

HSB is driven low by any means are given time to complete

before the STORE operation is initiated. After HSB goes low, the

STK14D88 will continue SRAM operations for t

, multiple SRAM READ operations may take place. If a

DELAY

WRITE is in progress when HSB is pulled low, it will be allowed

a time, t

, to complete. However, any SRAM WRITE cycles

DELAY

requested after HSB goes low will be inhibited until HSB returns

high.

If HSB is not used, it should be left unconnected.

Software STORE

Data can be transferred from the SRAM to the nonvolatile

memory by a software address sequence. The STK14D88

software STORE cycle is initiated by executing sequential E

controlled READ cycles from six specific address locations in

exact order. During the STORE cycle, previous data is erased

and then the new data is programmed into the nonvolatile

elements. Once a STORE cycle is initiated, further memory

inputs and outputs are disabled until the cycle is completed.

STK14D88

. During

DELAY

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