Cypress Semiconductor Perform STK16C88-3 Manual - Página 9

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Table 3. SRAM Write Cycle
Parameter
Cypress
Parameter
t
t
WC
AVAV
t
t
t
PWE
WLWH,
WLEH
t
t
t
SCE
ELWH,
ELEH
t
t
t
SD
DVWH,
DVEH
t
t
t
HD
WHDX,
EHDX
t
t
t
AW
AVWH,
AVEH
t
t
t
SA
AVWL,
AVEL
t
t
t
HA
WHAX,
EHAX
[7,8]
t
t
HZWE
WLQZ
[7]
t
t
LZWE
WHQX
Switching Waveforms
ADDRESS
CE
WE
DATA IN
DATA OUT
ADDRESS
CE
WE
DATA IN
DATA OUT
Notes
8. If WE is Low when CE goes Low, the outputs remain in the high impedance state.
9. CE or WE must be greater than V
Document Number: 001-50594 Rev. **
Alt
Write Cycle Time
Write Pulse Width
Chip Enable To End of Write
Data Setup to End of Write
Data Hold After End of Write
Address Setup to End of Write
Address Setup to Start of Write
Address Hold After End of Write
Write Enable to Output Disable
Output Active After End of Write
Figure 7. SRAM Write Cycle 1: WE Controlled
t
SA
PREVIOUS DATA
Figure 8. SRAM Write Cycle 2: CE Controlled
t
SA
t
AW
t
HIGH IMPEDANCE
during address transitions.
IH
Description
t
WC
t
SCE
t
AW
t
PWE
t
SD
DATA VALID
t
HZWE
HIGH IMPEDANCE
t
WC
t
SCE
PWE
t
SD
DATA VALID
STK16C88-3
35 ns
Min
Max
35
25
25
12
0
25
0
0
13
5
[9]
t
HA
t
HD
t
LZWE
[9]
t
HA
t
HD
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Page 9 of 14
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