Cypress Semiconductor STK14C88-3 Hoja de especificaciones - Página 2

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Pin Configurations

Table 1. Pin Definitions - 32-Pin SOIC/32-Pin PDIP
Pin Name
Alt
IO Type
A
–A
Input
0
14
DQ
-DQ
Input or
0
7
Output
Input
WE
W
Input
CE
E
Input
OE
G
V
Ground
SS
V
Power Supply Power Supply Inputs to the Device.
CC
Input or
HSB
Output
V
Power Supply AutoStore Capacitor. Supplies power to nvSRAM during power loss to store data from
CAP
Document Number: 001-50592 Rev. **
Figure 1. Pin Diagram - 32-Pin SOIC/32-Pin PDIP
Address Inputs. Used to select one of the 32,768 bytes of the nvSRAM.
Bidirectional Data IO lines. Used as input or output lines depending on operation.
Write Enable Input, Active LOW. When the chip is enabled and WE is LOW, data on the
IO pins is written to the specific address location.
Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the
chip.
Output Enable, Active LOW. The active LOW OE input enables the data output buffers
during read cycles. Deasserting OE HIGH causes the IO pins to tri-state.
Ground for the Device. The device is connected to ground of the system.
Hardware Store Busy (HSB). When LOW, this output indicates a Hardware Store is in
progress. When pulled low external to the chip, it initiates a nonvolatile STORE operation. A
weak internal pull up resistor keeps this pin high if not connected (connection optional).
SRAM to nonvolatile elements.
Description
STK14C88-3
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