Cypress Semiconductor STK22C48 Hoja de especificaciones - Página 2

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Pin Configurations

Table 1. Pin Definitions
Pin Name
Alt
IO Type
A
–A
Input
0
10
DQ
-DQ
Input or Output Bidirectional Data IO Lines. Used as input or output lines depending on operation.
0
7
Input
WE
W
Input
CE
E
Input
OE
G
V
Ground
SS
V
Power Supply Power Supply Inputs to the Device.
CC
Input or Output Hardware Store Busy (HSB). When LOW, this output indicates a Hardware Store is in progress.
HSB
V
Power Supply AutoStore Capacitor. Supplies power to nvSRAM during power loss to store data from SRAM
CAP
NC
No Connect
Document Number: 001-51000 Rev. **
Figure 1. Pin Diagram - 28-Pin SOIC
V
1
CAP
NC
2
A
3
7
A
6
4
A
5
5
28-SOIC
A
4
6
A
3
7
Top View
A
2
8
(Not To Scale)
A
9
1
A
0
10
DQ0
11
DQ1
12
DQ2
13
V
SS
14
Address Inputs. Used to select one of the 2,048 bytes of the nvSRAM.
Write Enable Input, Active LOW. When the chip is enabled and WE is LOW, data on the IO
pins is written to the specific address location.
Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.
Output Enable, Active LOW. The active LOW OE input enables the data output buffers during
read cycles. Deasserting OE HIGH causes the IO pins to tri-state.
Ground for the Device. The device is connected to ground of the system.
When pulled low external to the chip, it initiates a nonvolatile STORE operation. A weak internal
pull up resistor keeps this pin high if not connected (connection optional).
to nonvolatile elements.
No Connect. This pin is not connected to the die.
V
28
CC
WE
27
HSB
26
A
25
8
A
24
9
NC
23
OE
22
A
21
10
CE
20
DQ7
19
DQ6
18
DQ5
17
DQ4
16
DQ3
15
Description
STK22C48
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