Cypress Semiconductor Z9973 Hoja de especificaciones - Página 2
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Pin Description
Pin Number
Pin Name
11
PECL_CLK
12
PECL_CLK#
9
TCLK0
10
TCLK1
44, 46, 48, 50
QA(3:0)
32, 34, 36, 38
QB(3:0)
16, 18, 21, 23
QC(3:0)
29
FB_OUT
25
SYNC
42, 43
SELA(1,0)
40, 41
SELB(1,0)
19, 20
SELC(1,0)
5, 26, 27
FB_SEL(2:0)
52
VCO_SEL
31
FB_IN
6
PLL_EN
7
REF_SEL
8
TCLK_SEL
2
MR#/OE
14
INV_CLK
3
SCLK
4
SDATA
17, 22, 28,
VDDC
33,37, 45, 49
13
VDD
1, 15, 24, 30,
VSS
35, 39, 47, 51
Note:
2.
A bypass capacitor (0.1 F) should be placed as close as possible to each positive power (< 0.2"). If these bypass capacitors are not close to the pins, their
high-frequency filtering characteristics will be cancelled by the lead inductance of the traces.
Document #: 38-07089 Rev. *D
PWR
I/O Type
I
PU
PECL Clock Input.
I
PD PECL Clock Input.
I
PU
External Reference/Test Clock Input.
I
PU
External Reference/Test Clock Input.
VDDC
O
Clock Outputs. See Table 2 for frequency selections.
VDDC
O
Clock Outputs. See Table 2 for frequency selections.
VDDC
O
Clock Outputs. See Table 2 for frequency selections.
VDDC
O
Feedback Clock Output. Connect to FB_IN for normal operation. The
divider ratio for this output is set by FB_SEL(0:2). See Table 1. A bypass
delay capacitor at this output will control Input Reference/ Output Banks
phase relationships.
VDDC
O
Synchronous Pulse Output. This output is used for system synchroni-
zation. The rising edge of the output pulse is in sync with both the rising
edges of QA (0:3) and QC(0:3) output clocks regardless of the divider ratios
selected.
I
PU
Frequency Select Inputs. These inputs select the divider ratio at QA(0:3)
outputs. See Table 2.
I
PU
Frequency Select Inputs. These inputs select the divider ratio at QB(0:3)
outputs. See Table 2.
I
PU
Frequency Select Inputs. These inputs select the divider ratio at QC(0:3)
outputs. See Table 2.
I
PU
Feedback Select Inputs. These inputs select the divide ratio at FB_OUT
output. See Table 1.
I
PU VCO Divider Select Input. When set LOW, the VCO output is divided by
2. When set HIGH, the divider is bypassed. See Table 1.
I
PU
Feedback Clock Input. Connect to FB_OUT for accessing the
phase-locked loop (PLL).
I
PU
PLL Enable Input. When asserted HIGH, PLL is enabled. And when LOW,
PLL is bypassed.
I
PU
Reference Select Input. When HIGH, the crystal oscillator is selected. And
when LOW, TCLK (0,1) is the reference clock.
I
PU
TCLK Select Input. When LOW, TCLK0 is selected and when HIGH TCLK1
is selected.
I
PU
Master Reset/Output Enable Input. When asserted LOW, resets all of the
internal flip-flops and also disables all of the outputs. When pulled HIGH,
releases the internal flip-flops from reset and enables all of the outputs.
I
PU
Inverted Clock Input. When set HIGH, QC(2,3) outputs are inverted. When
set LOW, the inverter is bypassed.
I
PU
Serial Clock Input. Clocks data at SDATA into the internal register.
I
PU
Serial Data Input. Input data is clocked to the internal register to
enable/disable individual outputs. This provides flexibility in power
management.
3.3V Power Supply for Output Clock Buffers.
3.3V Supply for PLL.
Common Ground.
Pin Description
Z9973
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