EG&G ORTEC 414A Manual de funcionamiento y servicio - Página 9
Navegue en línea o descargue pdf Manual de funcionamiento y servicio para Amplificador EG&G ORTEC 414A. EG&G ORTEC 414A 15 páginas. Fast coincidence
Imprimir página5. CIRCUIT DESCRIPTION
(Etched Board 220 - 164)
The fast coincidence circuit consists of three identical
coincidence input stages and an anticoincidence input stage,
all feeding in parallel to a coincidence stage or AND gate
(see Drawings 414A-0164-S1 and 414A-0101-B1). The
coincidence stage is composed of transistors Q5, Q6, Q7,
and Q24, which constitute one side of a one-shot trigger
circuit, and Q8, which constitutes the other side. The
output of this trigger circuit is fed to Q9, where it is
inverted and sent to QlO and Q25, the output
emitter-followers.
The coincidence input signals are all regenerated in the
regeneration and pulse forming stages; for example,
coincidence Input A signal is regenerated by the one-shot
trigger circuit Q1 and 02 and is again reshaped and fed out
by the ac-coupled Schmitt trigger circuit 03 and 04 to 05,
The input signal is fed into regeneration circuit 01 and 02
through a 2-V limiter consisting of resistors R2, R3, R5,
and R8. The limiting action is-accomplished by switching
the constant current that normally flows through D2 and
R3 through limiter load resistor R5 by the application of a
positive input signal on Input A.
The 2t resolving time is set by the On duration of the
ac-coupled Schmitt trigger circuit 03 and 04. The signal
input to 03 is a negative-going pulse with a precisely
controlled amplitude from the collector of 01. The
negative-going pulse is coupled through C4 to the base of
03 and turns off 03. 03 remains off for a duration t. The
constant-current generator Oil and series resistor R12
control the duration, t, by discharging capacitor C4 back
from its negative value toward ground. When the voltage at
03 exceeds ground potential, 03 again is switched on and
04 is turned off. The duration that 04 remains on
constitutes one-half the resolving time, i.e., t. The output
of 04 is a negative-going pulse which turns off 05 in the
coincidence circuit and combination one-shot
multivibrator. The anticoincidence input has a similar
voltage limiter, a current switch (021 and 022), and a
voltage clamp which turns 024 on or off. The
anticoincidence circuit is dc-coupled from the input to
024; therefore 024 may be turned on by a pulse or a dc
voltage.
The combination of 05, 06, 07, and 024 constitutes one
side of a one-shot trigger circuit, with 08 constituting the
other side. 024, the anticoincidence input, is normally
biased off, while 05, 06, and 07, the coincidence inputs,
are normally biased on. In the event that 05, 06, and 07
are all turned off simultaneously and 024 is not turned on
by an anticoincidence input, the one-shot multivibrator
circuit is triggered, and 08 conducts the normal current
flowing through R26. A negative-going pulse is formed at
the collector of 08 and is inverted by 09. The output signal
of invertor 09 is fed through emitter-followers .010 and
024, and thence to the output BNC connectors.
The constant-current generator Oil generates a current
which is equal to 31. This current is then split into three
equal parts, with one part going to each of the three input
pulse-forming circuits, i.e., 03-04, 017-016, and 012-013.
Either A, B, or C front panel control switch (SI, S2, or S3)
can disable one coincidence input of the combination
threefold coincidence and one-shot multivibrator circuit
composed of 05, ,06, 07, 024, and 08 (see Drawing
414A-0101-S1). When one of these switches is moved to
Out, the transistor corresponding to that switch is
reverse-biased, resulting in a twofold coincidence circuit.
The actual coincidence recognition is performed by
transistors 05, 06, and 08, while 024 acts to inhibit the
coincidence output when a signal is applied to the
anticoincidence input. The anticoincidence input can be
disabled by placing switch D (S4) to the Out position. This
interrupts the signal to the anticoincidence circuit. With
front panel control switches A, B, and C all placed to In, a
current of approximately 3 mA flows through R26 and
then is passed through transistors 05, 06, and 07 in
parallel and thence through R23.
Moving switch A, B, or C to Out back-biases the particular
transistor associated with that switch, thus making the
series path consist of R26, the two remaining transistors,
and R23. With the application of simultaneous negative
input pulses to 05, 06, and 07 and in the absence of an
anticoincidence pulse to turn on 024, the current flow
through R23 ceases and a positive pulse is coupled through
CIO into the base of 08. 08 conducts for a time constant
determined by CIO and R24, thereby back-biasing the
parallel combination of 05, 06, and 07. Notice that in the
quiescent state 08 is back-biased by the voltage drop across
diode D9, since 09 is forward-biased with a current of 1
mA.