Jameco Atmel AT89C2051-12PI Manuel - Page 12
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Serial Port Timing: Shift Register Mode Test Conditions
= 5.0V ± 20%; Load Capacitance = 80 pF)
(V
CC
Symbol
Parameter
t
Serial Port Clock Cycle Time
XLXL
t
Output Data Setup to Clock Rising Edge
QVXH
t
Output Data Hold After Clock Rising Edge
XHQX
t
Input Data Hold After Clock Rising Edge
XHDX
t
Clock Rising Edge to Input Data Valid
XHDV
Shift Register Mode Timing Waveforms
AC Testing Input/Output Waveforms
Note:
1.
AC Inputs during testing are driven at V
a logic 1 and 0.45V for a logic 0. Timing measure-
ments are made at V
max. for a logic 0.
(1)
- 0.5V for
CC
min. for a logic 1 and V
IH
IL
12 MHz Osc
Min
Max
1.0
12t
700
10t
CLCL
50
2t
CLCL
0
700
Float Waveforms
Note:
1.
For timing purposes, a port pin is no longer float-
ing when a 100 mV change from load voltage
occurs. A port pin begins to float when 100 mV
change frothe loaded V
AT89C2051
Variable Oscillator
Min
Max
CLCL
-133
-117
0
10t
-133
CLCL
(1)
/V
level occurs.
OH
OL
Units
µs
ns
ns
ns
ns
4-25