Arcam RDAC - Manuel d'entretien - Page 8
Parcourez en ligne ou téléchargez le pdf Manuel d'entretien pour {nom_de_la_catégorie} Arcam RDAC -. Arcam RDAC - 14 pages. Wireless usb transmitter
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+5V
RX200
5V to 3.3V conversion
OC-0805R*007
IC200A
74LVC1G125
C200
Optical in
R200
R201
3
2
4
100N
O/P
16V
P208
47R
P209
P210
47R
0W063
0W063
DGND
DGND
D200
BAT54S
+3V3
DGND
SKT200
P219
2b
C202
P207
100N
16V
COAX in
R203
C204
1a
75R
100P
JYE TAI
0W063
50V
RJ
DGND
IC206A
74LVC1G125
P224
2
4
SERIAL_KLEER_TO_UC
P226
SERIAL_KLEER_TO_UC
R220
buffer tr-states serial
TX line of Kleer
UC_PROGRAM_MODE
module while in
10K
R213
programming mode
10K
0W063
DGND
DGND
+5V
SERIAL_UC_TO_KLEER
SERIAL_UC_TO_KLEER
P227
UART0_TX
CON202
+5V
UART0_RX
1
DGND
2
P240
C216
C217
C219
C220
C221
3
P241
4
10P
10P
10P
10P
10P
AMP
50V
50V
50V
50V
50V
CT
DGND
Use this connector to program
& debug the Kleer module
DGND
CON201
1
P236
KLEER_MCLK
2
3
P237
KLEER_BCLK
4
5
P238
KLEER_LRCLK
6
7
P239
KLEER_SDATA
8
R221
R222
R223
R224
SAMTEC
C222
C223
C224
C225
SLW
DGND
10P
10P
10P
10P
10K
10K
10K
10K
50V
50V
50V
50V
DGND
CON203
+5V
1
2
SERIAL_UC_TO_KLEER
3
SERIAL_KLEER_TO_UC
4
Use this connector to program
AMP
the Atmel microcontroller
CT
DGND
+3V3
IC200B
IC203E
+3V3
5
14
VCC
VCC
C215
C211
100N
10N
16V
50V
3
7
GND
GND
74HC125D
74LVC244ADB
DGND
DGND
SPDIF receiver
SDIN/HWMODE sets software control (pull up on other sheet)
SWIFMODE sets 2 wire software mode
CSB/GPO2 sets I2C address = 0111 010x
+3V3_SPDIF
3
RX0
P212
SPDIF_OPT
2
RX1
SPDIF_COAX
27
RX2
26
RX3
25
RX4/GPO3
24
RX5/GPO4
23
RX6/GPO5
22
RX7/GPO6
5
SPDIF_INT
GPO0/SWIFMODE
6
P211
GPO1
/RESET
10
/RESET
RESETB
P213
SCL
4
SCL
SCLK
P214
SDA
7
SDA
SDIN/HWMODE
R210
8
P245
SDOUT/GPO7
10K
9
CSB/GPO2
0W063
R211
10K
0W063
DGND
DGND
WM8805 decoupling
+3V3_SPDIF
DGND
KLEER BOARD
CON200
1
2
3
4
5
6
Oscillator for USB audio
7
spare
8
SDIN/HWMODE sets software control (pull up on other sheet)
SWIFMODE sets 2 wire software mode
SAMTEC
CSB/GPO2 sets I2C address = 0111 011x
SLW
+3V3OSC
3
RX0
2
RX1
27
RX2
26
RX3
25
RX4/GPO3
24
RX5/GPO4
23
RX6/GPO5
22
RX7/GPO6
5
GPO0/SWIFMODE
6
GPO1
/RESET
10
RESETB
SCL
4
SCLK
SDA
7
SDIN/HWMODE
R217
+3V3OSC
8
R218
SDOUT/GPO7
10K
9
CSB/GPO2
0W063
10K
0W063
DGND
DGND
WM8805 decoupling
+3V3OSC
C209
1UF
6.3V
DGND
+3V3
IC202C
+3V3
IC206B
+3V3
IC205C
20
5
VCC
VCC
20
VCC
C212
C213
C214
100N
100N
100N
16V
16V
16V
10
3
GND
GND
10
GND
74LVC244ADB
DGND
DGND
DGND
IC201
WM8805GEDS
17
DGND
DIN
16
P215
R204
47R
SPDIF_SDATA
P202
DOUT
20
MCLK
19
P216
R207
47R
SPDIF_LRCLK
P220
LRCLK
18
P217
R208
47R
SPDIF_BCLK
P221
BCLK
21
TX0
13
P244
R209
47R
SPDIF_MCLK
P222
CLKOUT
C201
15
P218
27P
XIN
50V
X200
14
12MHz
XOP
C203
27P
P223
50V
DGND
DGND
C205
C206
1UF
100N
6.3V
16V
MCLK MUX
ENABLE_SPDIF*
KLEER_MCLK
ENABLE_KLEER*
IC204
WM8805GEDS
17
DIN
16
DOUT
ENABLE_USB*
C218
20
DGND
MCLK
19
LRCLK
18
BCLK
15P
21
50V
DGND
TX0
13
R216
47R
MCLK_OSC
CLKOUT
P246
C207
15
P242
27P
XIN
50V
X201
14
11.2896MHz
XOP
C208
27P
P243
50V
DGND
C210
100N
16V
IC205B
19
OE*
3
Y0
17
5
A0
Y1
15
7
A1
Y2
13
9
A2
Y3
11
A3
74LVC244ADB
DGND
I2S MUX
IC202A
ENABLE_SPDIF*
1
ENABLE_SPDIF*
OE*
P230
18
Y0
2
16
A0
Y1
4
14
A1
Y2
6
12
A2
Y3
8
A3
74LVC244ADB
DGND
IC202B
ENABLE_USB*
19
ENABLE_USB*
OE*
P231
3
Y0
USB_SDATA
P232
17
5
USB_SDATA
A0
Y1
USB_LRCK
P233
15
7
USB_LRCK
A1
Y2
USB_BCK
P234
13
9
USB_BCK
A2
Y3
11
A3
74LVC244ADB
DGND
IC205A
ENABLE_KLEER*
1
ENABLE_KLEER*
OE*
P235
18
Y0
KLEER_SDATA
2
16
A0
Y1
KLEER_LRCLK
4
14
A1
Y2
KLEER_BCLK
6
12
A2
Y3
8
A3
74LVC244ADB
DGND
IC203A
R212
2
3
DAC_MCLK
DAC_MCLK
47R
74HC125D
IC203D
R219
12
11
P225
47R
74HC125D
IC203B
R214
5
6
47R
R228
74HC125D
10K
0W063
DGND
IC203C
R215
P228
9
8
USB_MCLK
P229
USB_MCLK
47R
74HC125D
Master clock for USB needs to be kept
at the appropriate frequency all the
time, even when SPDIF input is
selected
DGND
DRAWING TITLE
rDAC SPDIF & Clocks
Filename:
L198_CT2_SPDIF.SchDoc
ARCAM
Notes:
A & R Cambridge Ltd.
Pembroke Avenue
Waterbeach
Cambridge CB25 9QR
Contact Engineer:
Peter Kuell
Contact Tel:
(01223) 203207
P200
R202
47R
P201
DAC_SDATA
P203
R205
47R
P204
DAC_LRCK
P205
R206
47R
P206
DAC_BCK
R225
R226
R227
10K
10K
10K
0W063
0W063
0W063
LAYOUT NOTE:
Ensure the 2 LVC244s and the series
DGND
resistors are placed close together
10_E131
PK
14/09/10
EMC changes from Telnova
10_E122
PG
08/09/10
Change X200 to 12MHz
10_E066
PK
12/04/10
None to this sheet
ECO No.
INITIALS
DATE
DESCRIPTION OF CHANGE
L198CT
Printed:
22/09/2010
Sheet
3
of
5
A2
DRAWING NO.
2.0
1.1
1.0
ISSUE