Digilent Pmod CAN Manuel de référence - Page 6

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Pmod CAN Reference Manual
1. Send modify register SPI command (0x05)
2. Send the address of the control MCP_CANCTRL (0x0F)
3. Send a mask to get things prepared (0x80)
4. Send the command to place the module in config mode (0x80)
2. Set config rate and clock for CAN
1. Send a write SPI command (0x02)
2. Send the address of the register to modify followed by the value to set
3. Three registers are manipulated in this way with a variety of settings; for more details see
Section 4.4 (page 47) in the
speed of 250 kBPS with a CAN clock of 20 MHz.
1.
CNF1 (0x2A) set to 0x41
2.
CNF2 (0x29) set to 0xFB
3.
CNF3 (0x28) set to 0x86
3. Initiate can buffer filters and registers
1. Set the receive filters to either standard or extended identifiers
1.
For all standard inputs and in the demo code, set registers 0x00 through 0x0B, registers
0x10 through 0x1B, and registers 0x20 through 0x27 to a value of 0x00. The transmit
register flags and settings are also all cleared by setting registers 0x30 through 0x3D,
0x40 through 0x4D, and registers 0x50 through 0x5D to a value of 0x00. This can be
done for each register by performing the following steps:
2.
Send a write SPI command (0x02)
3.
Send the register address of interest
4.
Send the value to be written (0x00)
4. Set the CAN mode for any message type
1. Send modify register SPI command (0x05)
2. Send the address of the control RXB0CNTRL (0x60)
3. Send a mask to get things prepared (0x64)
4. Send the actual command to accept any message type (0x60)
5. Set CAN control mode to normal mode
1. Send modify register SPI command (0x05)
2. Send the address of the control MCP_CANCTRL (0x0F)
3. Send a mask to get things prepared (0x80)
4. Send the actual command to put in config mode (0x00)
2.3.2 Receive
1. Send the Read Status SPI command (0xA0) to see if any flags have been set. The Pmod will respond with a
single byte detailing a number of flags status as follows:
Bit 7* (MSB) is TX2IF Transmit Buffer 2 Empty interrupt Flag bit (bit 4 in CANINTF (0x2C)), must be
cleared by system to be reset
Bit 6 is TXREQ Message Transmit request bit (bit 3 in TXB2CTRL register 0x50) auto cleared on
message sent
Bit 5* is TX1IF Transmit Buffer 1 Empty interrupt Flag bit (bit 3 in CANINTF (0x2C)), must be
cleared by system to be reset
Bit 4 is TXREQ Message Transmit request bit (bit 3 in TXB1CTRL register 0x40) auto cleared on
message sent
Bit 3* is TX0IF Transmit Buffer 0 Empty interrupt Flag bit (bit 2 in CANINTF (0x2C)), must be
cleared by system to be reset
Copyright Digilent, Inc. All rights reserved.
Other product and company names mentioned may be trademarks of their respective owners.
MCP25625
datasheet. The following three commands set a CAN
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