Epson SED152A Series Manuel technique - Page 6

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Epson SED152A Series Manuel technique
Supply voltage
LCD voltage
Part number
range (V)
range (V)
SED1560D
0A
SED1560D
AA
SED1560D
0B
SED1560D
AB
SED1560T
0B
SED1560T
QA
SED1561D
0A
SED1561D
AA
SED1561D
2.4–6.0
6.0–16.0
0B
SED1561D
AB
SED1561T
0B
SED1561T
AB
SED1561T
QA
SED1562D
0A
SED1562D
0B
SED1562T
0B
SED1562T
QA
SED1565D
0B
SED1565D
*
1B
SED1565D
2B
SED1565T
0A
SED1565T
0B
SED1565T
0C
SED1566D
0B
SED1566D
*
1B
SED1566D
1.8–5.5
4.5–16.0
2B
SED1566T
0A
SED1567D
0B
SED1567D
*
1B
SED1567D
2B
SED1567T
0B
SED1567T
0C
SED1568D
0B
SED1569D
0B
SED1569T
**
SED1570D
0A
2.7–5.5
8.0–20.0
SED1570D
0B
SED1526D
*A
SED1526D
*B
SED1526F
*A
SED1526T
*A
2.4–6.0
Supply
SED1528D
*A
voltage
SED1528D
*B
SED1528F
*A
SED1528T
*A
Duty
Segment Common
1/48, 1/49
102
1/64, 1/65
1/24, 1/25
134
1/32, 1/33
1/16, 1/17
150
(1/5bias)
1/65
(1/7, 1/9 bias)
1/49
(1/6, 1/8 bias)
132
1/33
(1/5, 1/6 bias)
1/55 (1/6, 1/8 bias)
1/53
(1/6, 1/8 bias)
1/64–1/200
80
1/8, 1/9
1/16, 1/17
3.5–
3
1/32, 1/33
64
Display
Microprocessor
RAM (bits)
interface
65
166 65
bits
33
17
8-bit parallel
or Serial
65
49
132 65
bits
33
55
53
200 80
–
4-bit parallel
bits
17
80 33
8-bit parallel
bits
or Serial
33
Frequency
Package
(KHz)
Al pad chip
Al pad chip
Au bump chip
Au bump chip
TCP
QTCP
Al pad chip
Built-in power circuit for LCD
(voltage tripler)
Al pad chip
SED1560
18
Au bump chip
SED1560
SED1561
Au bump chip
SED1561
TCP
TCP
QTCP
Al pad chip
Au bump chip
TCP
QTCP
Au bump chip
Au bump chip
Au bump chip
TCP
TCP
TCP
Au bump chip
Au bump chip
Built-in power circuit for LCD
33
Au bump chip
(DC/DC 4)
TCP
Au bump chip
Au bump chip
Au bump chip
TCP
TCP
Au bump chip
Au bump chip
TCP
Al pad chip
–
Built-in self-refreshing function
Au bump chip
Built-in power circuit for LCD
Al pad chip
(voltage tripler)
Au bump chip
SED1526
(V
QFP5-128pin
SED1526
TCP
(no V
20
SED1526
Al pad chip
(redistribution of COMS)
Au bump chip
SED1528
(V
QFP5-128pin
SED1528
(no V
TCP
Application/additional
features
(1/9 bias)
0B
(1/7 bias)
AB
(1/7 bias)
0B
(1/5 bias)
AB
0
)
REG
E
)
REG
A
0
)
REG
E
)
REG