Toshiba TLP711E Manuel de formation technique - Page 10
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3-2-3. Alternation/Sample & Hold ICs
(Q401, Q402, Q501, Q502, Q601 and Q602)
The block diagram is shown in Fig. 3-2-3.
The main features of this circuit are as follows;
• High speed signal process for XGA signal
(Dot clock 100 MHz)
• Low output deviation owing to the output offset cancel
c i r c u i t b u i l t - i n
• No group delay time in inversion/non-inversion
• ECL configuration timing generator built-in
• Adjustable dot clock phase
• VCOM voltage generation circuit built-in
• Pre-charge pulse generation circuit built-in
Fig. 3-2-3 Block diagram of alternation/sample & hold IC
These ICs amplify the signals with gamma controlled and
supply the signals alternately. These signals are divided in
x 2 = 12 phase) and supplied to the LCD
6 phase signals (6
panel. Also, VCOM voltage and pre-charge signals required
for LCD panel are generated in these ICs.
The signal path is as follows:
The video signal entered pin 47 of Q401 (Q501 and Q601)
is amplified approx. 2.7 times by the INVERT AMP and
output from pin 46 of Q401 (Q501 and Q601). The signal
enters pins 45 of Q401 (Q501 and Q601) and Q402 (Q502
and Q602) and developed in 6 phase signals in each IC.
The signals 1 to 6 are processed by Q401 (Q501 and Q601)
and signals 7 to 12 by Q402 (Q502 and Q602).
3-3