Toshiba TLP711E Manuel de formation technique - Page 24
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6-2-2. Motion Adaptable Sequential Scanning Signal
Conversion Section
This section consists of the exclusive IC, QX300, and
three external field memory ICs of QX310, QX320 and
QX330.
By converting the interlace scanning signal of approx.
15.75 kHz into the sequential scanning signal of approx.
31.5 kHz, jitters on the screen is reduced.
The Y, V and U analog signals entered QX300 are
clamped by the internal clamp circuit and then converted
to the 8-bit digital signals by the A/D converter built-in.
The A/D clock is approx. 14.3 MHz for Y signal and
approx. 7.16 MHz for V and U signals.
The digital V and U signals are multi-processed and
converted to the digital VU multiplex signal.
In the sequential scanning signal conversion, the number of
scanning lines are converted from 262.5 lines/field to 525
lines/filed by inserting new scanning lines (scanning line
interpolation signal) between each interlace scanning line.
In the still mode, the scanning line interpolation signal is
generated by using one previous field signal for digital Y
signal in the field memory IC, QX310 and the digital VU
multiplex signal in the field memory IC, QX330.
In the motion picture mode, the scanning line interpola-
tion signal is generated by using upper and lower
scanning line signals in the line memory built-in.
Accordingly, since the video signal obtained after
processing the motion adaptable sequential scanning line
conversion is a signal consisting of two fields superim-
posed, you can obtain, especially in the still mode, a
clearer image without line flickers with the vertical
resolution improved.
The identification of still picture/motion picture on the
video signal is carried out by using the field memory IC,
QX320.
Thus processed digital Y/VU multiplex signals are
developed from pins 30 to 38 and 40 to 48 respectively
a s a n 8 - b i t s i g n a l .
6-2-3. Output Process Section
The output process section converts the 8-bit digital
signal to an analog signal and smoothes the video signal
waveform by using a low pass filter.
The digital Y/VU multiplex signals developed from
QX300 enter pins 18 to 25 and pins 9 to 16 and 18 to 25
of D/A converter IC, QX500, respectively.
The D/A clock signal for the Y signal enters from pin 67
of QX300 to pin 26 of QX500 through the inverter IC,
QX606. The D/A clock signal for the VU signal enters
pins 27 and 28 of QX500 from pins 52 and 50 of QX300.
The D/A clock for the Y signal is approx. 28.6 MHz and
for the VU signal, approx. 14.3 MHz. The digital VU
multiplex signal is converted into the analog V, U signals.
The Y, V, U signals of analog signal converted in QX500
develop from pins 36, 38 and 40 respectively. Then, each
signal passes through the low pass filter and enters to the
switching IC in the next stage.
6-2-4. Clock Signal Generation Section
This section generates the clock signal synchronized with
the input video signal by using the HD signal of pin 7 of
PV001 as a reference signal. The oscillation frequency is
approx. 28. 6 MHz in 1820 fH.
Pins 69 to 79 of QX300 is the PLL section for clock
signal generation.
6-2-5. Output Sync Signal
The HD and VD output signals develop from pins 28 and
27 of QX300 as a 3.3 V(p-p) signal.
To change the output level to 5 V(p-p), the TTL-CMOS
conversion IC, QX470, is used. The output signal is
supplied to the switching IC in the next stage.
In the same way, the BLKOUT signal develops from pin
26 of QX300 is changed to the 5 V(p-p) signal through
QX470.
The SCPout signal is developed by adding a 5 V(p-p)
signal processed by passing the CLPout signal developed
from pin 20 of QX300 through QX470 and MSKout
signal developed from pin 25.
2
6-2-6. I
C Bus
The process condition setting in QX300 is determined by
the clock signal and data passing through I
6-2
2
C bus.