Dimtel LLRF4.6 Manuel - Page 5

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LVDS inter-board communication
Since Spartan-6 supports internal differential termination for LVDS, on-board termination
resistors have been deleted. Direction and termination options can be specified in HDL
code now.
Unfortunately, Xilinx does not support bi-directional LVDS I/O with runtime termination
control. So the bit files have to explicitly define inputs and outputs, enabling termination
for the inputs. Since the signals are flipped on the cable, it is feasible to define 4 output
channels and 4 input channels, with identical bitfile on both FPGAs.

Connector Summary

Counterclockwise around the perimeter of the board
J101
SMA
J201
SMA
J301
SMA
J401
SMA
J15
SMA
J17
SMA
J7
34-pin header
J18
SMA
J19
SMA
J20
SMA
J9
24-pin header
J8
6-pin Weidmuller
J21
LEMO
J22
LEMO
J6
2.1 mm
J1
Type B
J3
20-pin 0.5mm flex
Interior test points
J23
U.Fl
J24
U.Fl
J25
U.Fl
J26
U.Fl
J27
2mm
J28
2mm
2mm test points are intended for use with a high-impedance single-ended FET scope probe.
RF/IF input
RF/IF input
RF/IF input
RF/IF input
LO input (+26 dBm nominal)
Clock input (+1 dBm nominal)
Geek port (see schematic)
RF/IF output
RF/IF output
Analog output (0 to 2.5V, 2.2 kΩ)
12 channels Analog output (0 to 2.5V)
SNS-compatible interlock I/O
Trigger
Trigger
+5V, 1.2A pseudo-regulated power input
USB
LVDS inter-board communication
LO monitor (remove R809 to maintain match)
ICS83940D output 17
ICS83940D output 4
AD9512 output 3
IF output channel 2
IF output channel 1
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