Pioneer CDJ-100S Manuel d'entretien - Page 39
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7. GENERAL INFORMATION
7.1 PARTS
7.1.1 IC
PD4977B (IC701: MOTHER BOARD ASSY)
System Control Micro-computer
Pin Assignment (Top view)
Block Diagram
TO0/P30
TI0/INTP0/P00
TO1/P31
TI1/P33
TO2/P32
TI2/P34
CI0/INTP3/P03
CI0/SB0/P25
CO0/SB1/P26
SCK0/P27
CI1/P20
SO1/P21
SCK1/P22
STB/P23
BUSY/P24
ANI0/P10 – ANI0/P17
AV
DD
AV
SS
AV
REF
INTP0/TI0/P00 – INTP3/CI0/P03
BUZ/P36
PCL/P35
P113/FIP21
65
P112/FIP20
66
P111/FIP19
67
P110/FIP18
68
P107/FIP17
69
P106/FIP16
70
V
71
LOAD
72
P105/FIP15
73
P104/FIP14
74
P103/FIP13
75
P102/FIP12
P101/FIP11
76
P100/FIP10
77
P97/FIP9
78
P96/FIP8
79
P95/FIP7
80
16-bit TIMER/
EVENT COUNTER
8-bit TIMER/
EVENT COUNTER 1
8-bit TIMER/
EVENT COUNTER 2
WATCHDOG TIMER
WATCH TIMER
6-bit UP/DOWN
COUNTER
SERIAL
INTERFACE 0
SERIAL
INTERFACE 1
A/D CONVERTER
INTERRUPT
CONTROL
BUZZER OUTPUT
CLOCK OUTPUT
CONTROL
¶ The information shown in the list is basic information and may
not correspond exactly to that shown in the schematic diagrams.
40
39
38
37
36
35
34
33
IC701
32
(PD4977B)
31
30
29
28
27
26
25
78K/0
ROM
CPU
CORE
RAM
FIP CONTROLLER/
V
V
IC
DD
SS
CDJ-100S
P33/TI1
P34/TI2
P35/PCL
P36/BUZ
P37
X2
X1
Vss
XT2
P04/XT1
AV
REF
AV
DD
P10/ANI0
P11/ANI1
P12/ANI2
P13/ANI3
P00
P01 – P03
PORT0
P04
PORT1
P10 – P17
P20 – P27
PORT2
PORT3
P30 – P37
PORT7
P70-P74
P80, P97
PORT8
PORT9
P90 – P97
PORT10
P100 – P107
P110 – P117
PORT11
PORT12
P120 – P127
FIP0 – FIP33
DRIVER
V
LOAD
RESET
X1
SYSTEM
X2
CONTROL
XT1/P04
XT2
39