Cypress F2MC-8FX Series Note d'application - Page 9
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4.3
Hardware Watchdog Timer
The hardware watchdog timer is set up through the following procedure:
Activate the watchdog timer by writing "A597
1.
(WDT is enabled in every mode) except other than "A596
flash memory, which are copied to the watchdog timer selection ID register WDTH/WDTL (0FEB
2.
The HWWDT starts automatically after a reset.
3.
Clear the watchdog timer with minimum interval time. (WDTC:WTE3 to WTE0 = 0101
Cause of while using the HWWDT, the count clock switch bits: CS1, CS0, CSP are fixed at "001", the interval time is
16
fixed at 2
/F
too.
CRL
The following example shows how to set watchdog timer for operating in hardware mode.
/* Hardware watchdog timer starts automatically after a reset and */
/* cannot be stopped. The internal time is fixed to 2
/* main routine */
void
main (void)
{
...
WDTC |= 0x05;
...
}
;------------------------------------------------------------------------
; Hard Watchdog
;------------------------------------------------------------------------
; #define HWD_DISABLE
#ifdef
#endif
main.c
startup.asm
Refer to Appendix Sample Code for project "HWWDT".
Please note that the hardware watchdog timer starts automatically after a reset and cannot stop its operation.
www.cypress.com
// clear WDT counter
HWD_DISABLE
.SECTION
WDT, CONST, LOCATE=H'FFBE
.DATA.W
0xA596
Document No. 002-05336 Rev.*A
F²MC-8FX Family, MB95200H/210H Series Watchdog Timer
" (WDT is enabled except in standby mode) or any other value
H
" and "A597
" to the address FFBE
H
H
16
/FCRL
and FFBF
on the
H
H
/0FEC
)
H
H
)
B
*/
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