Cypress Semiconductor AutoStore STK14CA8 Fiche technique - Page 6

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SRAM WRITE Cycles #1 and #2
Symbols
NO.
#1
#2
t
t
12
AVAV
AVAV
t
t
13
WLWH
WLEH
t
t
14
ELWH
ELEH
t
t
15
DVWH
DVEH
t
t
16
WHDX
EHDX
t
t
17
AVWH
AVEH
t
t
18
AVWL
AVEL
t
t
19
WHAX
EHAX
[5,7]
t
20
WLQZ
t
21
WHQX
ADDRESS
E
18
t
AVWL
W
DATA IN
DATA IN
DATA OUT
ADDRESS
E
W
DATA IN
DATA OUT
Notes
7. If W is low when E goes low, the outputs remain in the high impedance state.
E or W must be ≥ V
8.
during address transitions.
IH
Document Number: 001-51592 Rev. **
Parameter
Alt.
t
Write Cycle Time
WC
t
Write Pulse Width
WP
t
Chip Enable to End of Write
CW
t
Data Setup to End of Write
DW
t
Data Hold after End of Write
DH
t
Address Setup to End of Write
AW
t
Address Setup to Start of Write
AS
t
Address Hold after End of Write
WR
t
Write Enable to Output Disable
WZ
t
Output Active after End of Write
OW
Figure 8. SRAM WRITE Cycle #1: W Controlled
12
t
AVAV
14
t
ELWH
17
t
AVWH
13
t
WLWH
20
t
WLQZ
PREVIOUS DATA
Figure 9. SRAM WRITE Cycle #2: E Controlled
t
AVAV
18
14
t
t
AVEL
ELEH
17
t
AVEH
13
t
WLEH
STK14CA8-25 STK14CA8-35 STK14CA8-45
Min
Max
25
20
20
10
0
20
0
0
10
3
[7,8]
19
t
WHAX
15
16
t
t
DVWH
WHDX
DATA VALID
HIGH IMPEDANCE
[7,8]
12
t
EHAX
15
16
t
t
DVEH
EHDX
DATA VALID
HIGH IMPEDANCE
STK14CA8
Min
Max
Min
Max
35
45
25
30
25
30
12
15
0
0
25
30
0
0
0
0
13
15
3
3
21
t
WHQX
19
Page 6 of 16
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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