Cypress Semiconductor CY2291 Fiche technique - Page 7

Parcourez en ligne ou téléchargez le pdf Fiche technique pour {nom_de_la_catégorie} Cypress Semiconductor CY2291. Cypress Semiconductor CY2291 12 pages. Cypress three-pll general purpose eprom programmable clock generator specification sheet

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Switching Characteristics, Commercial 5.0V
Parameter
Name
t
Lock Time for
10B
UPLL and SPLL
Slew Limits
Switching Characteristics, Commercial 3.3V
Parameter
Name
t
Output Period
1
Output Duty
[11]
Cycle
t
Rise Time
3
t
Fall Time
4
t
Output Disable
5
Time
t
Output Enable
6
Time
t
Skew
7
t
CPUCLK Slew
8
[14]
t
Clock Jitter
9A
[14]
t
Clock Jitter
9B
[14]
t
Clock Jitter
9C
[14]
t
Clock Jitter
9D
t
Lock Time for
10A
CPLL
t
Lock Time for
10B
UPLL and SPLL
Slew Limits
Document #: 38-07189 Rev. *C
(continued)
Description
Lock Time from Power Up
CPU PLL Slew Limits
Description
Clock output range, 3.3V
operation
Duty cycle for outputs, defined as t
f
> 66 MHZ
OUT
Duty cycle for outputs, defined as t
f
< 66 MHZ
OUT
[13]
Output clock rise time
[13]
Output clock fall time
Time for output to enter three-state mode after
SHUTDOWN/OE goes LOW
Time for output to leave three-state mode after
SHUTDOWN/OE goes HIGH
Skew delay between any identical or related outputs
12, 15]
Frequency transition rate
Peak-to-peak period jitter (t
9A
clock period (f
< 4 MHz)
OUT
Peak-to-peak period jitter (t
9B
< f
< 16 MHz)
OUT
Peak-to-peak period jitter
(16 MHz < f
< 50 MHz)
OUT
Peak-to-peak period jitter
(f
> 50 MHz)
OUT
Lock Time from Power Up
Lock Time from Power Up
CPU PLL Slew Limits
CY2291
CY2291F
CY2291
(80 MHz)
CY2291F
(66.6 MHz)
÷ t
[12]
2
1
÷ t
[12]
2
1
[3,
Max. – t
min.),% of
9A
Max. – t
min.) (4 MHz
9B
CY2291
CY2291F
CY2291
Min.
Typ.
Max.
< 0.25
1
8
100
8
90
Min.
Typ.
Max.
12.5
13000
(76.923 kHz)
15
13000
(76.923 kHz)
40%
50%
60%
45%
50%
55%
3
5
2.5
4
10
15
10
15
< 0.25
0.5
1.0
20.0
<0.5
1
<0.7
1
<400
500
<250
350
<25
50
<0.25
1
8
80
8
66.6
Page 7 of 12
Unit
ms
MHz
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
MHz/m
s
%
ns
ps
ps
ms
ms
MHz
MHz
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