Cypress Semiconductor CY62167EV30 Fiche technique - Page 4

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Thermal Resistance

Tested initially and after any design or process changes that may affect these parameters.
Parameter
Description
Θ
Thermal Resistance
JA
(Junction to Ambient)
Θ
Thermal Resistance
JC
(Junction to Case)
Shaded areas contain preliminary information.
R1
V
CC
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
Parameters
R1
R2
R
TH
V
TH
Data Retention Characteristics
Over the Operating Range
Parameter
Description
V
V
for Data Retention
DR
CC
[10]
I
Data Retention Current
CCDR
[11]
t
Chip Deselect to Data
CDR
Retention Time
[12]
t
Operation Recovery Time
R
V
CC
or
CE
1
[13]
.
BHE
BLE
or
CE
2
Notes
11. Tested initially and after any design or process changes that may affect these parameters.
12. Full device operation requires linear V
13. BHE.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling the chip enable signals or by disabling both BHE and BLE.
Document #: 38-05446 Rev. *E
Test Conditions
Still Air, soldered on a 3 × 4.5 inch,
two-layer printed circuit board
Figure 3. AC Test Loads and Waveforms
V
R2
Rise Time = 1 V/ns
Equivalent to: THÉVENIN EQUIVALENT
OUTPUT
2.2V to 2.7V
16667
15385
8000
1.20
V
= 1.5V to 3.0V, CE
CC
1
− 0.2V or V
< 0.2V, V
> V
IN
CC
− 0.2V, CE
V
= 1.5V, CE
> V
CC
1
CC
− 0.2V or V
V
> V
IN
CC
IN
Figure 4. Data Retention Waveform
V
(min)
CC
t
CDR
(min) > 100 μs or stable at V
ramp from V
to V
CC
DR
CC
VFBGA
(6 x 7 x 1mm)
(6 x 8 x 1mm)
27.74
9.84
ALL INPUT PULSES
CC
90%
10%
GND
R
TH
V
2.7V to 3.6V
1103
1554
645
1.75
Conditions
− 0.2V, CE
> V
Industrial/
CC
2
Auto-A
< 0.2V
IN
< 0.2V,
Industrial -45BAXI/
2
< 0.2V
DATA RETENTION MODE
> 1.5 V
V
DR
(min) > 100 μs.
CC
CY62167EV30 MoBL
VFBGA
TSOP I
55
60
16
4.3
90%
10%
Fall Time = 1 V/ns
Unit
Ω
Ω
Ω
V
[5]
Min Typ
Max
1.5
-45ZXI
8
(TSOP I)
10
-45BVXI/
-45BVI
(VFBGA)
0
t
RC
V
(min)
CC
t
R
Page 4 of 14
®
Unit
°C/W
°C/W
Unit
V
μA
μA
ns
ns
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