Cypress Semiconductor CY7B9911V Fiche technique - Page 10

Parcourez en ligne ou téléchargez le pdf Fiche technique pour {nom_de_la_catégorie} Cypress Semiconductor CY7B9911V. Cypress Semiconductor CY7B9911V 15 pages. Cypress high speed low voltage programmable skew clock buffer specification sheet

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Switching Characteristics – 7 Option
[2, 11]
Over the Operating Range
Parameter
f
Operating Clock
NOM
Frequency in MHz
t
REF Pulse Width HIGH
RPWH
t
REF Pulse Width LOW
RPWL
t
Programmable Skew Unit
U
t
Zero Output Matched Pair Skew (XQ0, XQ1)
SKEWPR
t
Zero Output Skew (All Outputs)
SKEW0
t
Output Skew (Rise-Rise, Fall-Fall, Same Class Outputs)
SKEW1
t
Output Skew (Rise-Fall, Nominal-Inverted, Divided-Divided)
SKEW2
t
Output Skew (Rise-Rise, Fall-Fall, Different Class Outputs)
SKEW3
t
Output Skew (Rise-Fall, Nominal-Divided, Divided-Inverted)
SKEW4
t
Device-to-Device Skew
DEV
t
Propagation Delay, REF Rise to FB Rise
PD
t
Output Duty Cycle Variation
ODCV
t
Output HIGH Time Deviation from 50%
PWH
t
Output LOW Time Deviation from 50%
PWL
t
Output Rise Time
ORISE
t
Output Fall Time
OFALL
t
PLL Lock Time
LOCK
t
Cycle-to-Cycle Output
JR
Jitter
Notes
11. Test measurement levels for the CY7B9911V are TTL levels (1.5V to 1.5V). Test conditions assume signal transition times of 2 ns or less and output loading
as shown in the
AC Test Loads and Waveforms
12. Guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect these parameters.
13. SKEW is defined as the time between the earliest and the latest output transition among all outputs for which the same tU delay is selected when all are loaded
with 30 pF and terminated with 50Ω to VCC/2 (CY7B9911V).
14. tSKEWPR is defined as the skew between a pair of outputs (XQ0 and XQ1) when all eight outputs are selected for 0tU.
15. tSKEW0 is defined as the skew between outputs when they are selected for 0tU. Other outputs are divided or inverted but not shifted.
16. CL=0 pF. For CL=30 pF, tSKEW0=0.35 ns.
17. There are three classes of outputs: Nominal (multiple of tU delay), Inverted (4Q0 and 4Q1 only with 4F0 = 4F1 = HIGH), and Divided (3Qx and 4Qx only in
Divide-by-2 or Divide-by-4 mode).
18. tDEV is the output-to-output skew between any two devices operating under the same conditions (VCC ambient temperature, air flow, and so on.)
19. tODCV is the deviation of the output from a 50% duty cycle. Output pulse width variations are included in tSKEW2 and tSKEW4 specifications.
20. Specified with outputs loaded with 30 pF for the CY7B9911V-5 and -7 devices. Devices are terminated through 50Ω to VCC/2.tPWH is measured at 2.0V. tPWL
is measured at 0.8V.
21. tORISE and tOFALL measured between 0.8V and 2.0V.
22. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VCC is stable and within normal operating limits. This
parameter is measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits.
Document Number: 38-07408 Rev. *D
Description
FS = LOW
FS = MID
FS = HIGH
[13, 15]
[12, 18]
[19]
[20]
[20]
[20, 21]
[20, 21]
[22]
[12]
RMS
[12]
Peak
unless otherwise specified.
Min
[1, 2]
15
[1, 2]
25
[1, 2 , 3]
40
5.0
5.0
[13, 14]
[13, 17]
[13, 17]
[13, 17]
[13, 17]
–0.7
–1.2
0.15
0.15
CY7B9911V
3.3V RoboClock+™
CY7B9911V-7
Unit
Typ
Max
30
MHz
50
110
ns
ns
See
Table 1
0.1
0.25
ns
0.3
0.75
ns
0.6
1.0
ns
1.0
1.5
ns
0.7
1.2
ns
1.2
1.7
ns
1.65
ns
0.0
+0.7
ns
0.0
+1.2
ns
3
ns
3.5
ns
1.5
2.5
ns
1.5
2.5
ns
0.5
ms
25
ps
100
200
ps
Page 10 of 14
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