Cypress Semiconductor CY7C027V Fiche technique - Page 8

Parcourez en ligne ou téléchargez le pdf Fiche technique pour {nom_de_la_catégorie} Cypress Semiconductor CY7C027V. Cypress Semiconductor CY7C027V 19 pages. 3.3v 32k/64k x 16/18 dual-port static ram

Imprimer la page
Cypress Semiconductor CY7C027V Fiche technique
Switching Characteristics
Parameter
t
Data Hold From Write End
HD
[9, 10]
t
R/W LOW to High Z
HZWE
[9 ,10]
t
R/W HIGH to Low Z
LZWE
[36]
t
Write Pulse to Data Delay
WDD
[36]
t
Write Data Valid to Read Data Valid
DDD
[11]
Busy Timing
t
BUSY LOW from Address Match
BLA
t
BUSY HIGH from Address Mismatch
BHA
t
BUSY LOW from CE LOW
BLC
t
BUSY HIGH from CE HIGH
BHC
t
Port Setup for Priority
PS
t
R/W HIGH after BUSY (Slave)
WB
t
R/W HIGH after BUSY HIGH (Slave)
WH
[13]
t
BUSY HIGH to Data Valid
BDD
[11]
Interrupt Timing
t
INT Set Time
INS
t
INT Reset Time
INR
Semaphore Timing
t
SEM Flag Update Pulse (OE or SEM)
SOP
t
SEM Flag Write to Read Time
SWRD
t
SEM Flag Contention Window
SPS
t
SEM Address Access Time
SAA

Data Retention Mode

The
CY7C027V/027VN/027AV/028V
CY7037V/037AV/038V are designed with battery backup in
mind. Data retention voltage and supply current are guaranteed
over temperature. The following rules ensure data retention:
1. Chip enable (CE) must be held HIGH during data retention, within
V
to V
– 0.2V.
CC
CC
2. CE must be kept between V
the power up and power down transitions.
3. The RAM can begin operation >t
mum operating voltage (3.0 volts).
Notes
11. For information on port-to-port delay through RAM cells from writing port to reading port, refer to
12. Test conditions used are Load 1.
13. t
is a calculated parameter and is the greater of t
BDD
14. CE = V
, V
= GND to V
, T
CC
in
CC
A
Document #: 38-06078 Rev. *B
Over the Operating Range
Description
– 0.2V and 70% of V
during
CC
CC
after V
reaches the mini-
RC
CC
–t
(actual) or t
WDD
PWE
DDD
= 25° C. This parameter is guaranteed but not tested.
CY7C027V/027VN/027AV/028V
[6]
(continued)
CY7C027V/027VN/027AV/028V/
CY7C037V/037AV/038V
-15
Min
Max
Min
0
0
10
3
3
30
25
15
15
15
15
5
5
0
0
13
15
15
15
15
10
10
5
5
5
5
15
Timing
and
V
3.0V
CC
CE
Parameter
ICC
At VCC
DR1
Figure 11
waveform.
–t
(actual).
SD
CY7C037V/037AV/038V
-20
-25
Max
Min
Max
0
12
15
3
40
50
30
35
20
20
20
20
20
20
16
17
5
0
17
20
25
20
20
20
20
12
5
5
20
25
Data Retention Mode
3.0V
> 2.0V
V
CC
t
V
to V
– 0.2V
CC
CC
V
IH
[14]
Test Conditions
Max
= 2V
50
DR
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RC
Unit
μA
Page 8 of 18
[+] Feedback