Cypress Semiconductor CY7C1018CV33 Fiche technique - Page 3

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Cypress Semiconductor CY7C1018CV33 Fiche technique
AC Test Loads and Waveforms
R 317Ω
3.3V
OUTPUT
30 pF
(a)
High-Z characteristics:
R 317Ω
3.3V
OUTPUT
5 pF
(c)
Switching Characteristics
Parameter
Read Cycle
t
Read Cycle Time
RC
t
Address to Data Valid
AA
t
Data Hold from Address Change
OHA
t
CE LOW to Data Valid
ACE
t
OE LOW to Data Valid
DOE
t
OE LOW to Low-Z
LZOE
t
OE HIGH to High-Z
HZOE
t
CE LOW to Low-Z
LZCE
t
CE HIGH to High-Z
HZCE
[8]
t
CE LOW to Power-up
PU
[8]
t
CE HIGH to Power-down
PD
[9, 10]
Write Cycle
t
Write Cycle Time
WC
t
CE LOW to Write End
SCE
t
Address Set-up to Write End
AW
t
Address Hold from Write End
HA
t
Address Set-up to Write Start
SA
t
WE Pulse Width
PWE
t
Data Set-up to Write End
SD
t
Data Hold from Write End
HD
t
WE HIGH to Low-Z
LZWE
t
WE LOW to High-Z
HZWE
Notes:
4.
AC characteristics (except High-Z) for all speeds are tested using the Thèvenin load shown in Figure (a). High-Z characteristics are tested for all speeds using
the test load shown in Figure (c).
5.
Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V.
are specified with a load capacitance of 5 pF as in (d) of AC Test Loads. Transition is measured ± 500 mV from steady-state voltage.
6.
t
, t
, and t
HZOE
HZCE
HZWE
7.
At any given temperature and voltage condition, t
8.
This parameter is guaranteed by design and is not tested.
9.
The internal Write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a Write, and the transition of any of these
signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write.
10. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t
Document #: 38-05131 Rev. *D
[4]
3.0V
GND
R2
351Ω
Rise Time: 1 V/ns
R2
351Ω
Over the Operating Range
Description
Min.
[6, 7]
[7]
[6, 7]
[7]
[6, 7]
is less than t
HZCE
LZCE
ALL INPUT PULSES
90%
10%
(b)
[5]
-10
-12
Max.
Min.
10
12
10
3
3
10
5
0
0
5
3
3
5
0
0
10
10
12
8
9
8
9
0
0
0
0
7
8
5
6
0
0
3
3
5
, t
is less than t
, and t
is less than t
HZOE
LZOE
HZWE
and t
HZWE
SD
CY7C1018CV33
90%
10%
Fall Time: 1 V/ns
-15
Max.
Min.
Max.
15
12
15
3
12
15
6
7
0
6
7
3
6
7
0
12
15
15
10
10
0
0
10
8
0
3
6
7
for any given device.
LZWE
.
Page 3 of 7
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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