Cypress Semiconductor CY7C1218H Fiche technique - Page 12
Parcourez en ligne ou téléchargez le pdf Fiche technique pour {nom_de_la_catégorie} Cypress Semiconductor CY7C1218H. Cypress Semiconductor CY7C1218H 16 pages. Cypress 1-mbit (32k x36) pipelined sync sram specification sheet
Imprimer la pageSwitching Waveforms
[17, 19, 20]
Read/Write Cycle Timing
t CYC
CLK
t CH
t CL
t ADS
t ADH
ADSP
ADSC
t AS
t AH
A1
A2
ADDRESS
BWE,
BW[A:D]
t CES
t CEH
CE
ADV
OE
Data In (D)
High-Z
t CLZ
Data Out (Q)
Q(A1)
High-Z
Back-to-Back READs
Notes:
19. The data bus (Q) remains in High-Z following a Write cycle unless an ADSP, ADSC, or ADV cycle is performed.
20. GW is HIGH.
Document #: 38-05667 Rev. *B
(continued)
A3
A4
t WES
t WEH
t DS
t DH
t CO
D(A3)
t OEHZ
Q(A2)
Single WRITE
DON'T CARE
t OELZ
Q(A4)
Q(A4+1)
Q(A4+2)
BURST READ
UNDEFINED
CY7C1218H
A5
A6
D(A5)
D(A6)
Q(A4+3)
Back-to-Back
WRITEs
Page 12 of 16
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