Cypress Semiconductor CY7C1223H Fiche technique - Page 11

Parcourez en ligne ou téléchargez le pdf Fiche technique pour {nom_de_la_catégorie} Cypress Semiconductor CY7C1223H. Cypress Semiconductor CY7C1223H 17 pages. Cypress 2-mbit (128k x 18) pipelined dcd sync sram specification sheet

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Switching Waveforms

[16]
Read Timing
t CYC
CLK
t CH
t ADS
t ADH
ADSP
ADSC
t AS
t AH
ADDRESS
A1
GW, BWE,BW
[A:B]
t CES
t CEH
CE
ADV
OE
Data Out (Q)
High-Z
Note:
16. On this diagram, when CE is LOW, CE
Document #: 38-05674 Rev. *B
t CL
t ADS
t ADH
A2
t WES
t WEH
t ADVS
t ADVH
t OEV
t OELZ
t OEHZ
t
CLZ
Q(A2)
Q(A1)
t CO
Single READ
DON'T CARE
is LOW, CE
is HIGH and CE
1
2
3
ADV suspends burst
t CO
t DOH
Q(A2 + 1)
Q(A2 + 2)
BURST READ
UNDEFINED
is LOW. When CE is HIGH, CE
is HIGH or CE
1
CY7C1223H
A3
Burst continued with
new base address
Deselect
cycle
t CHZ
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
Q(A3)
Burst wraps around
to its initial state
is LOW or CE
is HIGH.
2
3
Page 11 of 16
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