Cypress Semiconductor CY7C1223H Fiche technique - Page 16

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Document History Page
Document Title: CY7C1223H 2-Mbit (128K x 18) Pipelined DCD Sync SRAM
Document Number: 38-05674
REV.
ECN NO. Issue Date
**
347357
See ECN
*A
424820
See ECN
*B
459347
See ECN
Document #: 38-05674 Rev. *B
Orig. of
Change
PCI
New Data Sheet
RXU
Changed address of Cypress Semiconductor Corporation on Page# 1 from
"3901 North First Street" to "198 Champion Court"
Changed Three-State to Tri-State.
Modified "Input Load" to "Input Leakage Current except ZZ and MODE" in the
Electrical Characteristics Table.
Modified test condition from V
Replaced Package Name column with Package Diagram in the Ordering
Information table.
Replaced Package Diagram of 51-85050 from *A to *B
NXR
Converted from Preliminary to Final
Included 2.5V I/O option
Updated the Ordering Information table.
CY7C1223H
Description of Change
< V
< V
to V
IH
DD
IH
DD
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