Cypress Semiconductor CY7C1344H Fiche technique - Page 3

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Pin Definitions
Name
I/O
A0, A1,
Input-
Address Inputs used to select one of the 64K address locations. Sampled at the rising edge of the
A
Synchronous
CLK if ADSP or ADSC is active LOW, and CE
counter.
BW
,
Input-
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct Byte Writes to the SRAM.
A
Synchronous
Sampled on the rising edge of CLK.
BW
B
BW
,
C
BW
D
GW
Input-
Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global
Synchronous
Write is conducted (ALL bytes are written, regardless of the values on BW
BWE
Input-
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be asserted
Synchronous
LOW to conduct a Byte Write.
CLK
Input-Clock
Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst
counter when ADV is asserted LOW, during a burst operation.
CE
Input-
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE
1
Synchronous
and CE
new external address is loaded.
CE
Input-
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE
2
Synchronous
and CE
CE
Input-
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE
3
Synchronous
and CE
OE
Input-
Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When LOW,
Asynchronous
the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data
pins. OE is masked during the first clock of a read cycle when emerging from a deselected state.
ADV
Input-
Advance Input signal, sampled on the rising edge of CLK. When asserted, it automatically incre-
Synchronous
ments the address in a burst cycle.
ADSP
Input-
Address Strobe from Processor, sampled on the rising edge of CLK, active LOW. When asserted
Synchronous
LOW, addresses presented to the device are captured in the address registers. A
into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is
ignored when CE
Input-
Address Strobe from Controller, sampled on the rising edge of CLK, active LOW. When asserted
ADSC
Synchronous
LOW, addresses presented to the device are captured in the address registers. A
into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized.
ZZ
Input-
ZZ "sleep" Input, active HIGH. When asserted HIGH places the device in a non-time-critical "sleep"
Asynchronous
condition with data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ
pin has an internal pull-down.
DQs
I/O-
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the
DQP
Synchronous
rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the
A,
DQP
addresses presented during the previous clock rise of the Read cycle. The direction of the pins is
B
DQP
controlled by OE . When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and
C,
DQP
DQP
D
V
Power
Power supply inputs to the core of the device.
DD
Supply
V
Ground
Ground for the core of the device.
SS
V
I/O Power
Power supply for the I/O circuitry.
DDQ
Supply
V
I/O Ground
Ground for the I/O circuitry.
SSQ
MODE
Input-
Selects Burst Order. When tied to GND selects linear burst sequence. When tied to V
Static
selects interleaved burst sequence. This is a strap pin and should remain static during device operation.
Mode pin has an internal pull-up.
NC
No Connects. Not Internally connected to the die. 4M, 9M,1 8M, 72M, 144M, 288M, 576M, and 1G are
address expansion pins and are not internally connected to the die.
Document #: 001-00211 Rev. *B
to select/deselect the device. ADSP is ignored if CE
3
to select/deselect the device. CE
3
to select/deselect the device. CE
2
is deasserted HIGH
1
are placed in a tri-state condition.
[A:D]
Description
, CE
, and CE
are sampled active. A
1
2
3
is HIGH. CE
1
is sampled only when a new external address is loaded.
2
is sampled only when a new external address is loaded.
3
CY7C1344H
feed the 2-bit
[1:0]
and BWE).
[A:D]
2
is sampled only when a
1
1
1
are also loaded
[1:0]
are also loaded
[1:0]
or left floating
DD
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