Cypress Semiconductor CY7C1346H Fiche technique - Page 12

Parcourez en ligne ou téléchargez le pdf Fiche technique pour {nom_de_la_catégorie} Cypress Semiconductor CY7C1346H. Cypress Semiconductor CY7C1346H 16 pages. 2-mbit (64k x 36) pipelined sync sram

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Switching Waveforms
[17, 18]
Write Cycle Timing
t CYC
CLK
t CH
t ADS
t ADH
ADSP
ADSC
t AS
t AH
ADDRESS
A1
Byte write signals are
ignored for first cycle when
ADSP initiates burst
BWE,
BW[A :D]
GW
t CES
t CEH
CE
ADV
OE
Data In (D)
High-Z
t
OEHZ
Data Out (Q)
BURST READ
Note:
18. Full width Write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW
Document #: 38-05672 Rev. *B
(continued)
t CL
t ADS
t ADH
A2
t WES
t DS
t DH
D(A2)
D(A2 + 1)
D(A1)
Single WRITE
DON'T CARE
ADSC extends burst
t WEH
ADV suspends burst
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
BURST WRITE
UNDEFINED
LOW.
[A:D]
CY7C1346H
t ADS
t ADH
A3
t WES
t WEH
t
t
ADVH
ADVS
D(A3)
D(A3 + 1)
D(A3 + 2)
Extended BURST WRITE
Page 12 of 16
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