Cypress Semiconductor CY7C1364C Fiche technique - Page 13

Parcourez en ligne ou téléchargez le pdf Fiche technique pour {nom_de_la_catégorie} Cypress Semiconductor CY7C1364C. Cypress Semiconductor CY7C1364C 19 pages. 9-mbit (256k x 32) pipelined sync sram

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Switching Waveforms
[18,19]
Write Cycle Timing
CLK
t ADS
t ADH
ADSP
ADSC
t AS
t AH
A1
ADDRESS
BWE,
BW[A :D]
GW
t CES
t CEH
CE
ADV
OE
Data In (D)
High-Z
Data Out (Q)
BURST READ
Note:
19. Full width Write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW
Document #: 38-05689 Rev. *E
(continued)
t CYC
t CH
t CL
t ADS
t ADH
A2
Byte write signals are
ignored for first cycle when
ADSP initiates burst
t DS
t DH
D(A1)
D(A2)
t
OEHZ
Single WRITE
DON'T CARE
ADSC extends burst
t WES
t WEH
ADV suspends burst
D(A2 + 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
BURST WRITE
UNDEFINED
LOW.
[A:D]
CY7C1364C
t ADS
t ADH
A3
t WES
t WEH
t
t
ADVS
ADVH
D(A3)
D(A3 + 1)
D(A3 + 2)
Extended BURST WRITE
Page 13 of 18
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