Cypress Semiconductor Perform CY62138CV33 Fiche technique - Page 6

Parcourez en ligne ou téléchargez le pdf Fiche technique pour {nom_de_la_catégorie} Cypress Semiconductor Perform CY62138CV33. Cypress Semiconductor Perform CY62138CV33 14 pages. 2-mbit (256k x 8) static ram mobl

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Cypress Semiconductor Perform CY62138CV33 Fiche technique

Switching Waveforms

Read Cycle 1 (Address transition controlled)
ADDRESS
DATA OUT
PREVIOUS DATA VALID
Read Cycle No. 2 (OE controlled)
ADDRESS
CE
OE
HIGH IMPEDANCE
DATA OUT
t
V
PU
CC
SUPPLY
CURRENT
Write Cycle No. 1 (WE controlled)
ADDRESS
CE
WE
OE
NOTE 20
DATA IO
Notes:
15. The device is continuously selected. OE, CE
16. WE is HIGH for read cycle.
17. Address valid before or similar to CE
18. Data IO is high impedance if OE = V
19. If CE
goes HIGH or CE
goes LOW simultaneously with WE HIGH, the output remains in high impedance state.
1
2
20. During this period, the IOs are in output state. Do not apply input signals.
Document #: 001-08029 Rev. *E
[15, 16]
t
AA
t
OHA
[10, 16, 17]
t
RC
t
ACE
t
DOE
t
LZOE
t
LZCE
50%
[10, 14, 18, 19]
t
SCE
t
AW
t
SA
t
HZOE
= V
, CE
= V
.
1
IL
2
IH
transition LOW and CE
transition HIGH.
1
2
.
IH
t
RC
RC
DATA VALID
t
WC
t
PWE
t
SD
DATA VALID
CY62138FV30 MoBL
DATA VALID
t
HZOE
t
HZCE
HIGH
IMPEDANCE
t
PD
50%
t
HA
t
HD
Page 6 of 13
®
I
CC
I
SB
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