Cypress Semiconductor Perform CY7C132 Manuel - Page 5

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Switching Characteristics
Over the Operating Range (Speeds -15, -25, -30)
Parameter
[12]
Write Cycle
t
Write Cycle Time
WC
t
CE LOW to Write End
SCE
t
Address Setup to Write End
AW
t
Address Hold from Write End
HA
t
Address Setup to Write Start
SA
t
R/W Pulse Width
PWE
t
Data Setup to Write End
SD
t
Data Hold from Write End
HD
t
R/W LOW to High Z
HZWE
t
R/W HIGH to Low Z
LZWE
Busy/Interrupt Timing
t
BUSY LOW from Address Match
BLA
t
BUSY HIGH from Address Mismatch
BHA
t
BUSY LOW from CE LOW
BLC
t
BUSY HIGH from CE HIGH
BHC
t
Port Set Up for Priority
PS
t
R/W LOW after BUSY LOW
WB
t
R/W HIGH after BUSY HIGH
WH
t
BUSY HIGH to Valid Data
BDD
t
Write Data Valid to Read Data Valid
DDD
t
Write Pulse to Data Delay
WDD
[16]
Interrupt Timing
t
R/W to INTERRUPT Set Time
WINS
t
CE to INTERRUPT Set Time
EINS
t
Address to INTERRUPT Set Time
INS
t
OE to INTERRUPT Reset Time
OINR
t
CE to INTERRUPT Reset Time
EINR
t
Address to INTERRUPT Reset Time
INR
Shaded areas contain preliminary information.
Notes
12. The internal write time of the memory is defined by the overlap of CE LOW and R/W LOW. Both signals must be LOW to initiate a write and either signal can terminate
a write by going HIGH. The data input setup and hold timing must be referenced to the rising edge of the signal that terminates the write.
13. These parameters are measured from the input signal changing, until the output pin goes to a high impedance state.
14. CY7C142/CY7C146 only.
15. A write operation on Port A, where Port A has priority, leaves the data on Port B's outputs undisturbed until one access time after one of the following:
BUSY on Port B goes HIGH.
Port B's address toggled.
CE for Port B is toggled.
R/W for Port B is toggled during valid read.
16. 52-pin PLCC and PQFP versions only.
Document #: 38-06031 Rev. *E
[8]
(continued)
Description
[7]
[7]
[13]
[13]
[14]
[13]
[13]
[13]
CY7C136A, CY7C142, CY7C146
7C132-25
[4]
7C136-15
7C136-25
7C146-15
7C142-25
7C146-25
Min
Max
Min
15
25
12
20
12
20
2
2
0
0
12
15
10
15
0
0
10
0
0
15
15
15
15
5
5
0
0
13
20
15
Note 15
Note 15
Note 15
Note 15
15
15
15
15
15
15
CY7C132, CY7C136
[4]
7C132-30
7C136-30
7C142-30
7C146-30
Max
Min
Max
30
25
25
2
0
25
15
0
15
15
0
20
20
20
20
20
20
20
20
5
0
30
25
30
Note 15
Note 15
25
25
25
25
25
25
25
25
25
25
25
25
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