Cypress Semiconductor Perform STK14D88 Manuel - Page 6

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SRAM WRITE Cycle #1 and #2
Symbols
NO.
#1
#2
12
t
t
AVAV
AVAV
13
t
t
WLWH
WLEH
14
t
t
ELWH
ELEH
15
t
t
DVWH
DVEH
16
t
t
WHDX
EHDX
17
t
t
AVWH
AVEH
18
t
t
AVWL
AVEL
19
t
t
WHAX
EHAX
[6, 8]
20
t
WLQZ
21
t
WHQX
ADDRESS
E
W
DATA IN
DATA OUT
ADDRESS
E
W
DATA IN
DATA OUT
Notes
8. If W is low when E goes low, the outputs remain in the high-impedance state.
≥
9. E or W must be
V
during address transitions.
IH
Document Number: 001-52037 Rev. **
Parameter
Alt.
t
Write Cycle Time
WC
t
Write Pulse Width
WP
t
Chip Enable to End of Write
CW
t
Data Set-up to End of Write
DW
t
Data Hold after End of Write
DH
t
Address Set-up to End of Write
AW
t
Address Set-up to Start of Write
AS
t
Address Hold after End of Write
WR
t
Write Enable to Output Disable
WZ
t
Output Active after End of Write
OW
Figure 6. SRAM WRITE Cycle 1: W Controlled
t
AVAV
14
t
ELWH
17
t
AVWH
18
t
AVWL
13
t
WLWH
20
t
WLQZ
PREVIOUS DATA
Figure 7. SRAM WRITE Cycle 2: E Controlled
18
t
AVEL
17
t
AVEH
STK14D88-25 STK14D88-35 STK14D88-45
Min
Max
25
20
20
10
0
20
0
0
10
3
[8, 9]
12
t
WHAX
15
13
t
t
DVWH
WHDX
DATA VALID
HIGH IMPEDANCE
[8, 9]
12
t
AVAV
14
t
ELEH
13
t
WLEH
15
t
DVEH
DATA VALID
HIGH IMPEDANCE
STK14D88
Min
Max
Min
Max
35
45
25
30
25
30
12
15
0
0
25
30
0
0
0
0
13
15
3
3
19
21
t
WHQX
19
t
EHAX
16
t
EHDX
Page 6 of 17
Unit
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