Cypress Semiconductor STK11C68 Fiche technique - Page 8

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SRAM Write Cycle
Parameter
Cypress
Alt
Parameter
t
t
WC
AVAV
t
t
t
PWE
WLWH,
WLEH
t
t
t
SCE
ELWH,
ELEH
t
t
t
SD
DVWH,
DVEH
t
t
t
HD
WHDX,
EHDX
t
t
t
AW
AVWH,
AVEH
t
t
t
SA
AVWL,
AVEL
t
t
t
HA
WHAX,
EHAX
[6,7]
t
t
HZWE
WLQZ
[6]
t
t
LZWE
WHQX
Switching Waveforms
ADDRESS
CE
WE
DATA IN
DATA OUT
ADDRESS
CE
WE
DATA IN
DATA OUT
Notes
7. If WE is Low when CE goes Low, the outputs remain in the high impedance state.
8. CE or WE must be greater than V
Document Number: 001-50638 Rev. **
Description
Write Cycle Time
Write Pulse Width
Chip Enable To End of Write
Data Setup to End of Write
Data Hold After End of Write
Address Setup to End of Write
Address Setup to Start of Write
Address Hold After End of Write
Write Enable to Output Disable
Output Active After End of Write
Figure 7. SRAM Write Cycle 1: WE Controlled
t
SA
PREVIOUS DATA
Figure 8. SRAM Write Cycle 2: CE and OE Controlled
t
SA
t
AW
t
PWE
HIGH IMPEDANCE
during address transitions.
IH
25 ns
Min
Max
25
20
20
10
0
20
0
0
10
5
t
WC
t
SCE
t
AW
t
PWE
t
SD
DATA VALID
t
HZWE
HIGH IMPEDANCE
t
WC
t
SCE
t
SD
DATA VALID
STK11C68
35 ns
45 ns
Min
Max
Min
35
45
25
30
25
30
12
15
0
0
25
30
0
0
0
0
13
5
5
[7, 8]
t
HA
t
HD
t
LZWE
[7, 8]
t
HA
t
HD
Unit
Max
ns
ns
ns
ns
ns
ns
ns
ns
15
ns
ns
Page 8 of 16
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