Cypress Semiconductor STK15C88 Fiche technique - Page 9

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Table 3. SRAM Write Cycle
Parameter
Cypress
Alt
Parameter
t
t
WC
AVAV
t
t
t
PWE
WLWH,
WLEH
t
t
t
SCE
ELWH,
ELEH
t
t
t
SD
DVWH,
DVEH
t
t
t
HD
WHDX,
EHDX
t
t
t
AW
AVWH,
AVEH
t
t
t
SA
AVWL,
AVEL
t
t
t
HA
WHAX,
EHAX
[7,8]
t
t
HZWE
WLQZ
[7]
t
t
LZWE
WHQX
Switching Waveforms
ADDRESS
CE
WE
DATA IN
DATA OUT
ADDRESS
CE
WE
DATA IN
DATA OUT
Notes
8. If WE is Low when CE goes Low, the outputs remain in the high impedance state.
9. CE or WE must be greater than V
Document Number: 001-50593 Rev. **
Description
Write Cycle Time
Write Pulse Width
Chip Enable To End of Write
Data Setup to End of Write
Data Hold After End of Write
Address Setup to End of Write
Address Setup to Start of Write
Address Hold After End of Write
Write Enable to Output Disable
Output Active After End of Write
Figure 7. SRAM Write Cycle 1: WE Controlled
t
SA
PREVIOUS DATA
Figure 8. SRAM Write Cycle 2: CE Controlled
t
SA
t
AW
t
HIGH IMPEDANCE
during address transitions.
IH
Min
t
WC
t
SCE
t
AW
t
PWE
t
SD
DATA VALID
t
HZWE
HIGH IMPEDANCE
t
WC
t
SCE
PWE
t
SD
DATA VALID
STK15C88
25 ns
45 ns
Max
Min
Max
25
45
20
30
20
30
10
15
0
0
20
30
0
0
0
0
10
15
5
5
[8]
t
HA
t
HD
t
LZWE
[8]
t
HA
t
HD
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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