Cypress Semiconductor Z9973 Fiche technique
Parcourez en ligne ou téléchargez le pdf Fiche technique pour {nom_de_la_catégorie} Cypress Semiconductor Z9973. Cypress Semiconductor Z9973 10 pages. 3.3v, 125-mhz, multi-output zero delay buffer
Imprimer la pageFeatures
• Output frequency up to 125 MHz
• 12 clock outputs: frequency configurable
• 350 ps max output-to-output skew
• Configurable output disable
• Two reference clock inputs for dynamic toggling
• Oscillator or PECL reference input
• Spread spectrum-compatible
• Glitch-free output clocks transitioning
• 3.3V power supply
• Pin-compatible with MPC973
• Industrial temperature range: –40°C to +85°C
• 52-pin TQFP package
Block Diagram
PECL_CLK
PECL_CLK#
VCO_SEL
PLL_EN
REF_SEL
Phase
TCLK0
0
Detector
1
TCLK1
LPF
TCLK_SEL
FB_IN
FB_SEL2
MR#/OE
Power-On
Reset
/4, /6, /8, /12
/4, /6, /8, /10
2
SELA(0,1)
/2, /4, /6, /8
2
SELB(0,1)
/4, /6, /8, /10
2
SELC(0,1)
Sync Pulse
2
FB_SEL(0,1)
Data Generator
SCLK
Output Disable
Circuitry
SDATA
INV_CLK
Cypress Semiconductor Corporation
Document #: 38-07089 Rev. *D
3.3V, 125-MHz, Multi-Output Zero Delay Buffer
Sync
D Q
Frz
0
VCO
1
Sync
D Q
Frz
Sync
D Q
Frz
Sync
D Q
Frz
0
Sync
D Q
/2
1
Frz
Sync
D Q
Frz
12
•
3901 North First Street
[1]
Table 1. Frequency Table
VC0_SEL
FB_SEL2
FB_SEL1
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
Note:
1.
x = the reference input frequency, 200 MHz < F
.
Pin Configuration
QA0
QA1
QA2
QA3
52 51 50 49 48 47 46 45 44 43 42 41 40
VSS
QB0
1
MR#/OE
2
QB1
SCLK
3
QB2
SDATA
4
FB_SEL2
5
QB3
PLL_EN
6
Z9973
REF_SEL
7
TCLK_SEL
8
QC0
TCLK0
9
TCLK1
10
QC1
11
PECL_CLK
QC2
12
PECL_CLK#
13
VDD
QC3
14 15 16 17 18 19 20 21 22 23 24 25 26
FB_OUT
SYNC
•
San Jose
•
Z9973
FB_SEL0
F
VC0
0
0
8x
0
1
12x
1
0
16x
1
1
20x
0
0
16x
0
1
24x
1
0
32x
1
1
40x
0
0
4x
0
1
6x
1
0
8x
1
1
10x
0
0
8x
0
1
12x
1
0
16x
1
1
20x
< 480 MHz.
VCO
VSS
39
QB0
38
VDDC
37
QB1
36
VSS
35
QB2
34
VDDC
33
QB3
32
FB_IN
31
VSS
30
29
FB_OUT
28
VDDC
27
FB_SEL0
CA 95134
•
408-943-2600
Revised December 21, 2002
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