Bose 3-2-1GS Series II Panduan Pemecahan Masalah - Halaman 24
Jelajahi secara online atau unduh pdf Panduan Pemecahan Masalah untuk Sistem Teater Rumah Bose 3-2-1GS Series II. Bose 3-2-1GS Series II 28 halaman. Home entertainment system
Halaman Cetak
THEORY OF OPERATION
2.2.2.7 S/PDIF Receiver
U4400 [sheet 1, B7] provides the S/PDIF digital audio receiver function. The incoming differen-
tial S/PDIF signal is fed to U4400's differential inputs RXP0 and RXN0 through a filter and
termination network. T1 is a common-mode transformer which rejects unwanted common-
mode noise, particularly important since U4400 has little or no common-mode rejection inherent
to the IC design. D4502 [sheet 3, C6] clamps the signal to +/- one diode drop. This is the only
"termination" of the input signal. The assumption is that while there is a termination mismatch
on the end of the twisted pair, all reflections and standing waves are eliminated by the clamping
action of the diodes, i.e., the reflections never reach into the +/- one diode drop region. The
subsequent resistors and capacitors form a low pass network that limits the bandwidth to just
above the fundamental bit rate of the S/PDIF signal (128Fs).
U4400 provides the system MCLK at 128Fs when the S/PDIF input is active. When the ADC
path is selected, the MCLK is provided by the DSP (U7000) SHRAC_CLK output [sheet 1, C3],
which is routed through U4400s MCLK output (pin 10) by setting the IC into "Stop" mode via an
I2C command from the DSP.
2.2.2.8 Internal audio path
External analog and S/PDIF input signals are converted to serial digital samples that are
clocked at the bit rate established by BITCLK. Each sample is 32-bits long alternate between
left and right channels as indicated by the LRCLK signal. The Codec, U4000, generates
BITCLK and LRCLK in all operating modes based on its MCLK input. MCLK is programmed to
be 128 times the LRCLK rate and, thus, 4 times the BITCLK rate.
The S/PDIF decoder, U4400, either generates MCLK from the bit-rate detected on the selected
digital audio input, or passes through the SHARC_CLK signal when no valid digital audio input
is detected or when the part is not running. The SHARC_CLK signal clocks the audio path
when analog audio inputs are selected.
The analog data converted by U4000 is presented to the DSP controller U7000 on A/DOUT.
The received digital data from either S/PDIF input is transmitted to U7000 on a separate signal
using the DR0A input of U7000. Both signals share the same LRCLK and BITCLK as do the
audio outputs D/ADATA1-3.
2.2.2.9 Communications
Smart Speaker Interface
Smart Speaker commands from the console are received by the circuit comprised of Q6100 and
Q6101 [sheet 1, C7]. The input is level shifted to a 3.3V signal by Q6100 and is then "gained-
up" with hysteresis before being presented to the PWM0 input of the DSP. This is accomplished
with 3 inverters of U6100 and C6105 and is necessary as the PWM0 input uses a fast counter
to determine the commands and any noise/glitching of the input destroys the message.
TAP Interface
The components used to access TAP directly onto the bass module DSP/Amplifier PCB are not
populated on the production versions of this board. Any testing or troubleshooting will be per-
formed using the Smart Speaker commands as listed in the test procedures in this troubleshoot-
ing guide. The following is for informational purposes only.
The TAP interface uses the serial ports (signals TAPIN and TAPOUT) on the Sharc micropro-
cessor (U7000 [sheet 1, C4]). The connection is made through J6200 [sheet 3, A8]. Q6200,
R6200 and similar convert RS-232 level input communication signals to logic level. Q6201
drives the output line to 0 and 3.3V. These parts are not used, and are shown as NV (no value)
on the schematic sheets.
24