DAQ system USB3-SDI01 Panduan Pengguna - Halaman 7

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2.3 SW1 Setting

 SDO_EN/DIS --- Control Signal Input/ Signal levels are LVCMOS / LVTTL compatible
When SDO_EN/DIS is LOW, the serial digital output signals SDO and SDO
are disabled and become high impedance.
When SDO_EN/DIS is HIGH, the serial digital output signals SDO and SDO
are enabled.
 RATE_SEL1..0 --- Control Signal Input/ Signal levels are LVCMOS / LVTTL compatible
RATE_SEL0
 DETECT_TRS --- Control Signal Input/ Signal levels are LVCMOS / LVTTL compatible
When DETECT_TRS is LOW, the device extracts all internal timing from
the supplied H:V:F or CEA-861 timing signals, depending on the status of
the TIM861 pin.
When DETECT_TRS is LOW, the device extracts all internal timing from
the TRS signals embedded in supplied video stream.
ON
1 2 3 4
[Figure 2-4. SW1 switch]
It is used to enable/disable the Serial Digital Output Stage.
It is used to configure the operating data rate.
RATE_SEL1
0
0
1
It is used to select external HVF or TRS extracting timing mode.
Data Rate
0
1.485 or 1.485/1.00GB/s
1
2.97 or 2.97/1.00GB/s
0
270Mb/s
7-
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ADP-SDI01 User's Manual(Rev(1.1)
http://www.daqsystem.com