Fujitsu MB91460 SERIES Catatan Aplikasi - Halaman 15

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2.4.1.3 Burst Transfer

For the burst transfer mode, MOD[1:0] bits of DMABA needs to be set as B'01.

1. In case of block transfer after the transfer request is received, transfer is carried out

continuously as specified by the transfer count and then the transfer is stopped. If

WS[1:0] of DMABA is B'10, BLK[3:0] of DMACA is B'1010 and DTC[15:0] is 0x10

then transfer would be carried out continuously until 160 (32-bit)words are

transferred.

2. DTC[15:0] bits of DMACA register would get decremented to 0.

3. After this the DMASA, DMADA registers gets updated accordingly.

4. Once the DTC[15:0] becomes 0, the transfer is stopped with DSS[1:0] of DMABA

5. The peripheral interrupt, if any, which had initiated the transfer request, gets cleared

by DMAC.

6. If the reload is enabled then the DMAC waits for next transfer request.

7. During this time the CPU can get access of the buses until the DMAC gets next

transfer request.

2.4.1.4 Demand Transfer

For the demand transfer mode, MOD[1:0] bits of DMABA needs to be set as B'10. The

number of block remain always 1 and the BLK[3:0] bit setting of DMACA is ignored. The

transfer source should be selected as high level or low level at DMAC external pin (DREQ)

by configuring IS[4:0] bits of DMACA register as B'01110 or B'01111 respectively. As long

as the level at the DREQ pin is maintained as per the configuration of IS[4:0] bits, the

transfer request is considered to be active.

1. In case of demand transfer after the transfer request is received (that is the signal

level at the DREQ pin is as per as per the configuration of IS[4:0] bits), a single

transfer is performed. If WS[1:0] of DMABA is B'10 then one (32-bit) word would be

transferred.

2. DTC[15:0] bits of DMACA register gets decremented by 1.

3. After this the DMASA, DMADA registers gets updated accordingly.

4. If the transfer request is not active anymore then the DMAC waits for the transfer

request (configured level at DREQ). During this time the CPU can get access of the

buses until the DMAC gets next transfer request.

5. If the transfer request is still active steps 1 to 3 are repeated until the DTC[15:0]

becomes 0.

6. Once the DTC[15:0] becomes 0, the transfer is stopped with DSS[1:0] of DMABA

7. The peripheral interrupt, if any, which had initiated the transfer request, gets cleared

by DMAC.

8. If the reload is enabled then the DMAC waits for next transfer request.

DIRECT MEMORY ACCESS

Chapter 2 Direct Memory Access

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MCU-AN-300059-E-V11