DG UDP10G-IP Setup Manual - Halaman 13

Jelajahi secara online atau unduh pdf Setup Manual untuk Motherboard DG UDP10G-IP. DG UDP10G-IP 18 halaman. Fpga setup with cpu demo

dg_toeudp10gip_fpgasetup_intel.doc

The step to setup test environment by using two FPGAs is described in more details as

follows.

Follow step 1) – 5) of topic 1 (Test environment setup when using FPGA and PC) to prepare

FPGA board.

Warning: For Arria10 SoC board, Clock controller for programming clock to 322.265625 MHz

could be used when only one FPGA is connected to PC. User connects one micro USB cable

to set clock on one Arria 10 SoC board at a time. If two Arria 10 SoC boards are used in the

test, user must switch micro USB cable to program clock on the 2

board setting. After that, two micro USB cables for connecting two FPGA boards to PC are

allowed.

1) Connect 10Gb Ethernet cable between two FPGA boards.

26-Aug-20

Figure 2-2 SFP+ transceiver connection

board after finishing the

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