Dell PowerEdge M910 Panduan Teknis - Halaman 10

Jelajahi secara online atau unduh pdf Panduan Teknis untuk Beralih Dell PowerEdge M910. Dell PowerEdge M910 46 halaman. M-series blade servers
Juga untuk Dell PowerEdge M910: Manual Pembaruan (44 halaman), Manual Pembaruan (21 halaman), Manual Pembaruan (14 halaman), Panduan Instalasi (7 halaman), Manual Pembaruan (28 halaman), Panduan Memulai (12 halaman), Panduan Memulai (12 halaman), Panduan Portofolio (27 halaman), Panduan Teknis (45 halaman), Panduan Memulai (14 halaman), Panduan Memulai (12 halaman), Panduan Teknis (49 halaman)

Halaman Cetak

Dell

Key Technologies

2.1 Overview

The PowerEdge M910 implements a number of new technologies:



Intel

Xeon

E7-2800, E7-4800, and E7-8800 product family



Intel 7510 Chipset

The PowerEdge M910 also implements the following key technologies:



FlexMem Bridge



IO Hub (IOH) with Intel



DDR3 memory



PCI Express

Generation 2



Optional Redundant SD media for embedded hypervisor



Integrated Dell Remote Access Controller 6 (iDRAC6) Express

2.2 Detailed Information

2.2.1

Intel 7510 Chipset

The 7510 chipset is designed to support Intel Xeon E7-2800, E7-4800, and E7-8800 product family,

Intel Xeon processor 6500 and 7500 series 4S family, Intel

memory technology, and PCI Express Generation 2 (PCIe G2).

2.2.2

Intel Processors

Key features of the Intel Xeon E7-2800, E7-4800, and E7-8800 product family include:



Up to ten cores per processor



Up to 30MB shared L3 cache



32 nm process technology



Intel Trusted Execution Technology (TXT) and AESNI (AES New Instructions)



RAS DDDC (Double Device Data Correct)



Intel HyperThreading (2 threads/core)

Key features of the Intel Xeon processor 6500 and 7500 series include:



Up to eight cores per processor



Four full-width, bidirectional point-to-point Intel QuickPath Interconnect (QPI) links at 6.4

GT/s



Four Intel

Scalable Memory Interconnects (SMI) at 6.4 GT/s



Socket: LS, LGA 1567 package



No termination required for non-populated processors (must populate processor socket 1 first)



64-byte cache line size



RISC/CISC hybrid architecture



Compatible with existing x86 code base



Optimized for 32-bit code



MMX support



Execute Disable Bit



Intel

Wide Dynamic Execution (Executes up to four instructions per clock cycle)



Simultaneous Multi-Threading (SMT) capability (2 threads/core)



Support for CPU Turbo Mode on certain SKUs (Increases processor frequency if operating

below thermal, power, and current limits)

PowerEdge M910 Technical Guide

QuickPath Architecture

QuickPath Interconnect

(QPI), DDR3