CIRCUIT DESIGN LMD-400-R Panduan Pengoperasian - Halaman 5

Jelajahi secara online atau unduh pdf Panduan Pengoperasian untuk Transceiver CIRCUIT DESIGN LMD-400-R. CIRCUIT DESIGN LMD-400-R 20 halaman. Uhf narrow band multi channel transceiver 438-442/458-462 mhz

Halaman Cetak
Receiver part
Item
Receiver type
1st IF frequency
2nd IF frequency
Maximum input level
BER (0 error/2556 bits)
*2
BER (1 % error)
Sensitivity 12dB/ SINAD
Co-channel rejection
Spurious response rejection
Adjacent CH selectivity
Blocking
Intermodulation
DO output level
RSSI rising time
Time until valid Data-out
st
Spurious radiation (1
RSSI
Notice
The time required until a stable DO is established may get longer due to the possible frequency drift
caused by operation environment changes, especially when switching from TX to RX, from RX to TX and
changing channels. Please make sure to optimize the timing. The recommended preamble is more than
20 ms.
Antenna connection is designed as pin connection.
RF output power, sensitivity, spurious emission and spurious radiation levels may vary with the pattern
used between the RF pin and the coaxial connection. Please make sure to verify those parameters
before use.
The feet of the shield case should be soldered to the wide GND pattern to avoid any change in
characteristics.
Notes about the specification values
*1 BER: RF level where no error per 2556 bits is confirmed with the signal of PN9 and 4800 bps.
*2 BER (1 % error) : RF level where 1% error per 2556 bits is confirmed with the signal of PN9 and 4800 bps.
*3 Spurious response, CH selectivity: The deviation of the unwanted signal is 12% of the channel separation
(=1.5kHz). Modulation frequency is 400Hz.
*4 Time until valid Data-out : Valid DO is determined at the point where Bit Error Rate meter starts detecting
the signal of 4800 bps, 1010repeated signal.
All specifications are specified based on the data measured in a shield room using the PLL setting controller
board prepared by Circuit Design.
OG_LMD-400-R-AB_v11e
MIN
Double superheterodyne
MHz
kHz
dBm
*1
dBm
dBm
dBm
dB
*3
dB
*3
dB
dB
dB
V
ms
*4
ms
Lo)
dBm
200
mV
130
TYP
MAX
Remarks
21.7
450
10
-107
PN 9 4800bps
-110
PN 9 4800bps
-110
fm1 k/ dev 2.4 kHz CCITT
-7
D/U ratio
70
1 st Mix, 2 signal method, 1 % error
70
2 nd Mix, 2 signal method, 1 % error
60
12.5 kHz ch, 2 signal method, 1 % error
Unwanted signal +/-1M, 2 signal method,
84
1 % error
65
3 signal method, 1 % error
2.8
L = GND H = 2.8 V
30
50
CH shift of 25 kHz (from PLL setup)
50
70
When power ON (from PLL setup)
50
100
CH shift of 25 kHz (from PLL setup)
70
120
When power ON (from PLL setup)
-60
-57
Conducted 50
270
340
With -100 dBm
200
270
Wi
Specifications are subject to change without prior notice
5
OPERATION GUIDE
h -110 dBm
ｔ
Circuit Design, Inc.