Siemens SIMATIC ET 200SP Manual - Halaman 24

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Parameters/address space

4.5 Address space

Chronological sequence

The figure shows the chronological sequence for oversampling. The output data present in

the CPU is output in the data cycle after the next one, distributed across the sub-cycles

which are generated on the actual module.

①

Figure 4-1

4.5

Address space

Configuration options

The following configurations are possible:

● Configuration 1: Without value status

● Configuration 2: With value status

Evaluating the value status

An additional byte is occupied in the input address space if you enable the value status for

the analog module. Bit 0 and 1 in this byte are assigned to the module. They provide

information about the validity of the analog value.

Bit =1: No fault is present on the channel.

Bit =0: The wiring, the value created on the channel, or similar is incorrect.

n = output values from bus cycle n

Oversampling

Analog output module AQ 2xU/I HS (6ES7135-6HB00-0DA1)

Manual, 09/2016, A5E03576140-AD