Cisco VIP4-50= Panduan Instalasi dan Konfigurasi - Halaman 5
Jelajahi secara online atau unduh pdf Panduan Instalasi dan Konfigurasi untuk Perangkat Keras Jaringan Cisco VIP4-50=. Cisco VIP4-50= 44 halaman. Fourth generation versatile interface processor
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Table 2
components.
Note
You can use any combination of available CPU memory configurations and packet memory
configurations on the VIP4. You do not need to have equal amounts of CPU memory and packet memory
installed. (For information about upgrading memory, see the
page
Table 2
VIP4 Model Features
Packets Forwarding
1
Product
(PPS)
VIP4-50 ~140,000
VIP4-80 ~170,000
1. PPS = Packets per Second
Table 3
VIP4 Internal Components
Type
Size/Speed
CPU (for VIP4-50) 200 megahertz (MHz)
internal operating frequency
CPU (for VIP4-80) 250 megahertz (MHz)
internal operating frequency
1
SDRAM DIMMs
64 (default), 128, or 256 MB
(program or CPU
memory)
1
SDRAM DIMMs
64 MB
(packet memory)
1. 8-bit error correction code (ECC), rather than byte parity, for single error-bit correction and double error-bit detection
OL-3673-01
outlines features of the VIP4 models, and
31.)
Distributed Switching/
Bandwidth
Services (DSW)
750+ MB
Yes;
Moderate to high DSW
750+ MB
Yes;
Very high DSW
Fourth Generation Versatile Interface Processor (VIP4) Installation and Configuration Guide
Table 3
provides a list of the VIP4 internal
Usage
Distributed switching
Moderate link utilization
Cisco Express Forwarding (CEF)
High distributed switching performance
Multiple high-speed PAs with high link utilization
Extensive use of distributed IP services
Cisco Content Networking (CCN)
Description
Reduced Instruction Set Computer (RISC),
IPSR5271 processor
Reduced Instruction Set Computer (RISC),
MIPS R7000 processor
100-MHz synchronous dynamic random-access
memory (SDRAM) as CPU memory contained on
dual in-line memory modules (DIMMs)
100-MHz synchronous dynamic random-access
memory (SDRAM) as packet memory contained on
dual in-line memory modules (DIMMs)
"Upgrading VIP4 Memory" section on
VIP4 Overview
Location
(see
Figure
1)
CPU
CPU
U1
U5
5