Cisco UCS C480 M5 Manual - Halaman 8
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Memory Configurations and Modes
nd
Table 2 2
Generation Intel
socket)
DIMM
to
DCPMM
Count
Channel 2
M2
M1
6 to 2
DIMM
6 to 4
DIMM
6 to 6
DCPMM
DIMM
Notes:
1. All systems must be fully populated with four CPUs when using DCPMMs at this time.
Four CPUs must be installed when using DCPMMs.
■
For Memory Mode and App Direct Mode, install a minimum 2 DCPMMs and 6 DIMMs per CPU
■
When either Memory Mode or Mixed Mode is used, the recommended ratio of DIMM capacity to
■
DCPMM capacity is between 1:16 and 1:4, and 1:4 achieves the best performance. For example, 6x
16 GB DIMMs + 2x 256 GB DCPMMs is a capacity ratio of 1:5.33 (96GB:512GB). In Mixed Mode, the
ratio is between memory and only the volatile portion of the DCPMMs. This ratio requirement does
not apply to App Direct mode. See
Table 3
Intel
®
Optane
®
TM
Intel
Optane
DC Persistent Memory Modes
App Direct Mode:
1
Memory Mode:
Mix Mode:
Notes:
1. For Memory Mode, the Intel-recommended DIMM to DCPMM capacity ratio in the same CPU socket is from 1:4 to
1:16.
For each memory channel with both a DCPMM and a DIMM installed, the DCPMM is installed in
■
channel slot 2 (closest to the CPU) and the DIMM is installed in channel slot 1.
To maximize performance, balance all memory channels
■
In configurations with DCPMMs installed, memory mirroring is supported, with two restrictions:
■
8
®
®
Xeon
Scalable Processor DIMM and DCPMM
iMC1
Channel 1
Channel 0
L2
L1
K2
DIMM
DCPMM
DCPMM
DIMM
DCPMM
DCPMM
DIMM
DCPMM
Table 3
TM
DC Persistent Memory Modes
DCPMM operates as a solid-state disk storage device. Data is saved and is
non-volatile. Both DCPMM and DIMM capacity counts towards CPU tiering
(both DCPMM and DIMM capacities count towards the CPU capacity limit)
DCPMM operates as a 100% memory module. Data is volatile and DRAM acts
as a cache for DCPMMs. Only DCPMM capacity counts towards CPU tiering
(only the DCPMM capacity counts towards the CPU capacity limit). This is
the factory default mode.
DRAM as cache. Only DCPMM capacity counts towards CPU tiering (only the
DCPMM capacity counts towards the CPU capacity limit).
CPU 4 (upper bay)
Channel 2
K1
J2
J1
DIMM
DIMM
DIMM
DIMM
DIMM
DCPMM
DIMM
for DCCPM memory modes.
1
Physical Configurations (quad
iMC0
Channel 1
Channel 0
H2
H1
G2
DIMM
DCPMM
DCPMM
DIMM
DCPMM
DCPMM
DIMM
DCPMM
Cisco UCS C480 M5 Memory Guide
G1
DIMM
DIMM
DIMM